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Commit e6d69a60 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma 

Pull slave-dmaengine changes from Vinod Koul:
 "This brings for slave dmaengine:

   - Change dma notification flag to DMA_COMPLETE from DMA_SUCCESS as
     dmaengine can only transfer and not verify validaty of dma
     transfers

   - Bunch of fixes across drivers:

      - cppi41 driver fixes from Daniel

      - 8 channel freescale dma engine support and updated bindings from
        Hongbo

      - msx-dma fixes and cleanup by Markus

   - DMAengine updates from Dan:

      - Bartlomiej and Dan finalized a rework of the dma address unmap
        implementation.

      - In the course of testing 1/ a collection of enhancements to
        dmatest fell out.  Notably basic performance statistics, and
        fixed / enhanced test control through new module parameters
        'run', 'wait', 'noverify', and 'verbose'.  Thanks to Andriy and
        Linus [Walleij] for their review.

      - Testing the raid related corner cases of 1/ triggered bugs in
        the recently added 16-source operation support in the ioatdma
        driver.

      - Some minor fixes / cleanups to mv_xor and ioatdma"

* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (99 commits)
  dma: mv_xor: Fix mis-usage of mmio 'base' and 'high_base' registers
  dma: mv_xor: Remove unneeded NULL address check
  ioat: fix ioat3_irq_reinit
  ioat: kill msix_single_vector support
  raid6test: add new corner case for ioatdma driver
  ioatdma: clean up sed pool kmem_cache
  ioatdma: fix selection of 16 vs 8 source path
  ioatdma: fix sed pool selection
  ioatdma: Fix bug in selftest after removal of DMA_MEMSET.
  dmatest: verbose mode
  dmatest: convert to dmaengine_unmap_data
  dmatest: add a 'wait' parameter
  dmatest: add basic performance metrics
  dmatest: add support for skipping verification and random data setup
  dmatest: use pseudo random numbers
  dmatest: support xor-only, or pq-only channels in tests
  dmatest: restore ability to start test at module load and init
  dmatest: cleanup redundant "dmatest: " prefixes
  dmatest: replace stored results mechanism, with uniform messages
  Revert "dmatest: append verify result to results"
  ...
parents 5a1efc6e df12a317

Documentation/devicetree/bindings/dma/atmel-dma.txt

+1 −1
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ The three cells in order are: 
dependent:

  - bit 7-0: peripheral identifier for the hardware handshaking interface. The

  identifier can be different for tx and rx.

  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.

  - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.



Example:

Documentation/devicetree/bindings/powerpc/fsl/dma.txt

+101 −37
Original line number Diff line number Diff line 
* Freescale 83xx DMA Controller

* Freescale DMA Controllers



Freescale PowerPC 83xx have on chip general purpose DMA controllers.

** Freescale Elo DMA Controller

   This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx

   series chips such as mpc8315, mpc8349, mpc8379 etc.



Required properties:



- compatible        : compatible list, contains 2 entries, first is

		 "fsl,CHIP-dma", where CHIP is the processor

		 (mpc8349, mpc8360, etc.) and the second is

		 "fsl,elo-dma"

- reg               : <registers mapping for DMA general status reg>

- ranges		: Should be defined as specified in 1) to describe the

		  DMA controller channels.

- compatible        : must include "fsl,elo-dma"

- reg               : DMA General Status Register, i.e. DGSR which contains

                      status for all the 4 DMA channels

- ranges            : describes the mapping between the address space of the

                      DMA channels and the address space of the DMA controller

- cell-index        : controller index.  0 for controller @ 0x8100

- interrupts        : <interrupt mapping for DMA IRQ>

- interrupts        : interrupt specifier for DMA IRQ

- interrupt-parent  : optional, if needed for interrupt mapping





- DMA channel nodes:

        - compatible        : compatible list, contains 2 entries, first is

			 "fsl,CHIP-dma-channel", where CHIP is the processor

			 (mpc8349, mpc8350, etc.) and the second is

			 "fsl,elo-dma-channel". However, see note below.

        - reg               : <registers mapping for channel>

        - cell-index        : dma channel index starts at 0.

        - compatible        : must include "fsl,elo-dma-channel"

                              However, see note below.

        - reg               : DMA channel specific registers

        - cell-index        : DMA channel index starts at 0.



Optional properties:

        - interrupts        : <interrupt mapping for DMA channel IRQ>

        - interrupts        : interrupt specifier for DMA channel IRQ

                              (on 83xx this is expected to be identical to

                              the interrupts property of the parent node)

        - interrupt-parent  : optional, if needed for interrupt mapping
@@ -70,30 +67,27 @@ Example: 
		};

	};



* Freescale 85xx/86xx DMA Controller



Freescale PowerPC 85xx/86xx have on chip general purpose DMA controllers.

** Freescale EloPlus DMA Controller

   This is a 4-channel DMA controller with extended addresses and chaining,

   mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as

   mpc8540, mpc8641 p4080, bsc9131 etc.



Required properties:



- compatible        : compatible list, contains 2 entries, first is

		 "fsl,CHIP-dma", where CHIP is the processor

		 (mpc8540, mpc8540, etc.) and the second is

		 "fsl,eloplus-dma"

- reg               : <registers mapping for DMA general status reg>

- compatible        : must include "fsl,eloplus-dma"

- reg               : DMA General Status Register, i.e. DGSR which contains

                      status for all the 4 DMA channels

- cell-index        : controller index.  0 for controller @ 0x21000,

                                         1 for controller @ 0xc000

- ranges		: Should be defined as specified in 1) to describe the

		  DMA controller channels.

- ranges            : describes the mapping between the address space of the

                      DMA channels and the address space of the DMA controller



- DMA channel nodes:

        - compatible        : compatible list, contains 2 entries, first is

			 "fsl,CHIP-dma-channel", where CHIP is the processor

			 (mpc8540, mpc8560, etc.) and the second is

			 "fsl,eloplus-dma-channel". However, see note below.

        - cell-index        : dma channel index starts at 0.

        - reg               : <registers mapping for channel>

        - interrupts        : <interrupt mapping for DMA channel IRQ>

        - compatible        : must include "fsl,eloplus-dma-channel"

                              However, see note below.

        - cell-index        : DMA channel index starts at 0.

        - reg               : DMA channel specific registers

        - interrupts        : interrupt specifier for DMA channel IRQ

        - interrupt-parent  : optional, if needed for interrupt mapping



Example:
@@ -134,6 +128,76 @@ Example: 
		};

	};



** Freescale Elo3 DMA Controller

   DMA controller which has same function as EloPlus except that Elo3 has 8

   channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx

   series chips, such as t1040, t4240, b4860.



Required properties:



- compatible        : must include "fsl,elo3-dma"

- reg               : contains two entries for DMA General Status Registers,

                      i.e. DGSR0 which includes status for channel 1~4, and

                      DGSR1 for channel 5~8

- ranges            : describes the mapping between the address space of the

                      DMA channels and the address space of the DMA controller



- DMA channel nodes:

        - compatible        : must include "fsl,eloplus-dma-channel"

        - reg               : DMA channel specific registers

        - interrupts        : interrupt specifier for DMA channel IRQ

        - interrupt-parent  : optional, if needed for interrupt mapping



Example:

dma@100300 {

	#address-cells = <1>;

	#size-cells = <1>;

	compatible = "fsl,elo3-dma";

	reg = <0x100300 0x4>,

	      <0x100600 0x4>;

	ranges = <0x0 0x100100 0x500>;

	dma-channel@0 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x0 0x80>;

		interrupts = <28 2 0 0>;

	};

	dma-channel@80 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x80 0x80>;

		interrupts = <29 2 0 0>;

	};

	dma-channel@100 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x100 0x80>;

		interrupts = <30 2 0 0>;

	};

	dma-channel@180 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x180 0x80>;

		interrupts = <31 2 0 0>;

	};

	dma-channel@300 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x300 0x80>;

		interrupts = <76 2 0 0>;

	};

	dma-channel@380 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x380 0x80>;

		interrupts = <77 2 0 0>;

	};

	dma-channel@400 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x400 0x80>;

		interrupts = <78 2 0 0>;

	};

	dma-channel@480 {

		compatible = "fsl,eloplus-dma-channel";

		reg = <0x480 0x80>;

		interrupts = <79 2 0 0>;

	};

};



Note on DMA channel compatible properties: The compatible property must say

"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA

driver (fsldma).  Any DMA channel used by fsldma cannot be used by another

Documentation/dmatest.txt

+41 −31
Original line number Diff line number Diff line
@@ -15,39 +15,48 @@ be built as module or inside kernel. Let's consider those cases. 


	Part 2 - When dmatest is built as a module...



After mounting debugfs and loading the module, the /sys/kernel/debug/dmatest

folder with nodes will be created. There are two important files located. First

is the 'run' node that controls run and stop phases of the test, and the second

one, 'results', is used to get the test case results.



Note that in this case test will not run on load automatically.



Example of usage:

	% modprobe dmatest channel=dma0chan0 timeout=2000 iterations=1 run=1



...or:

	% modprobe dmatest

	% echo dma0chan0 > /sys/module/dmatest/parameters/channel

	% echo 2000 > /sys/module/dmatest/parameters/timeout

	% echo 1 > /sys/module/dmatest/parameters/iterations

	% echo 1 > /sys/kernel/debug/dmatest/run

	% echo 1 > /sys/module/dmatest/parameters/run



...or on the kernel command line:



	dmatest.channel=dma0chan0 dmatest.timeout=2000 dmatest.iterations=1 dmatest.run=1



Hint: available channel list could be extracted by running the following

command:

	% ls -1 /sys/class/dma/



After a while you will start to get messages about current status or error like

in the original code.

Once started a message like "dmatest: Started 1 threads using dma0chan0" is

emitted.  After that only test failure messages are reported until the test

stops.



Note that running a new test will not stop any in progress test.



The following command should return actual state of the test.

	% cat /sys/kernel/debug/dmatest/run



To wait for test done the user may perform a busy loop that checks the state.



	% while [ $(cat /sys/kernel/debug/dmatest/run) = "Y" ]

	> do

	> 	echo -n "."

	> 	sleep 1

	> done

	> echo

The following command returns the state of the test.

	% cat /sys/module/dmatest/parameters/run



To wait for test completion userpace can poll 'run' until it is false, or use

the wait parameter.  Specifying 'wait=1' when loading the module causes module

initialization to pause until a test run has completed, while reading

/sys/module/dmatest/parameters/wait waits for any running test to complete

before returning.  For example, the following scripts wait for 42 tests

to complete before exiting.  Note that if 'iterations' is set to 'infinite' then

waiting is disabled.



Example:

	% modprobe dmatest run=1 iterations=42 wait=1

	% modprobe -r dmatest

...or:

	% modprobe dmatest run=1 iterations=42

	% cat /sys/module/dmatest/parameters/wait

	% modprobe -r dmatest



	Part 3 - When built-in in the kernel...
@@ -62,21 +71,22 @@ case. You always could check them at run-time by running 


	Part 4 - Gathering the test results



The module provides a storage for the test results in the memory. The gathered

data could be used after test is done.

Test results are printed to the kernel log buffer with the format:



The special file 'results' in the debugfs represents gathered data of the in

progress test. The messages collected are printed to the kernel log as well.

"dmatest: result <channel>: <test id>: '<error msg>' with src_off=<val> dst_off=<val> len=<val> (<err code>)"



Example of output:

	% cat /sys/kernel/debug/dmatest/results

	dma0chan0-copy0: #1: No errors with src_off=0x7bf dst_off=0x8ad len=0x3fea (0)

	% dmesg | tail -n 1

	dmatest: result dma0chan0-copy0: #1: No errors with src_off=0x7bf dst_off=0x8ad len=0x3fea (0)



The message format is unified across the different types of errors. A number in

the parens represents additional information, e.g. error code, error counter,

or status.

or status.  A test thread also emits a summary line at completion listing the

number of tests executed, number that failed, and a result code.



Comparison between buffers is stored to the dedicated structure.

Example:

	% dmesg | tail -n 1

	dmatest: dma0chan0-copy0: summary 1 test, 0 failures 1000 iops 100000 KB/s (0)



Note that the verify result is now accessible only via file 'results' in the

debugfs.
 
The details of a data miscompare error are also emitted, but do not follow the

above format.

arch/arm/common/edma.c

+2 −2
Original line number Diff line number Diff line
@@ -404,7 +404,7 @@ static irqreturn_t dma_irq_handler(int irq, void *data) 
					BIT(slot));

			if (edma_cc[ctlr]->intr_data[channel].callback)

				edma_cc[ctlr]->intr_data[channel].callback(

					channel, DMA_COMPLETE,

					channel, EDMA_DMA_COMPLETE,

					edma_cc[ctlr]->intr_data[channel].data);

		}

	} while (sh_ipr);
@@ -459,7 +459,7 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data) 
								callback) {

						edma_cc[ctlr]->intr_data[k].

						callback(k,

						DMA_CC_ERROR,

						EDMA_DMA_CC_ERROR,

						edma_cc[ctlr]->intr_data

						[k].data);

					}

arch/arm/include/asm/hardware/iop3xx-adma.h

+0 −30
Original line number Diff line number Diff line
@@ -393,36 +393,6 @@ static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt, 
	return slot_cnt;

}



static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc)

{

	return 0;

}



static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,

					struct iop_adma_chan *chan)

{

	union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };



	switch (chan->device->id) {

	case DMA0_ID:

	case DMA1_ID:

		return hw_desc.dma->dest_addr;

	case AAU_ID:

		return hw_desc.aau->dest_addr;

	default:

		BUG();

	}

	return 0;

}





static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc,

					  struct iop_adma_chan *chan)

{

	BUG();

	return 0;

}



static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,

					struct iop_adma_chan *chan)

{