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Commit e6d46f79 authored by Krishna Manikandan's avatar Krishna Manikandan
Browse files

disp: msm: stage layer with zorder 0 as base layer 



Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.

Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
parent 7e8a5f7e

msm/sde/sde_crtc.c

+26 −6
Original line number Diff line number Diff line
@@ -2479,7 +2479,7 @@ static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate, 
		user_cfg = &dim_layer_v1.layer_cfg[i];



		dim_layer[i].flags = user_cfg->flags;

		dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0;

		dim_layer[i].stage = user_cfg->stage;



		dim_layer[i].rect.x = user_cfg->rect.x1;

		dim_layer[i].rect.y = user_cfg->rect.y1;
@@ -4117,7 +4117,7 @@ static void sde_crtc_enable(struct drm_crtc *crtc, 


/* no input validation - caller API has all the checks */

static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state,

		struct plane_state pstates[], int cnt)

		struct plane_state pstates[], int cnt, bool base_layer_staged)

{

	struct sde_crtc_state *cstate = to_sde_crtc_state(state);

	struct drm_display_mode *mode = &state->adjusted_mode;
@@ -4144,6 +4144,8 @@ static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state, 
					mode->vdisplay);

			rc = -E2BIG;

			goto end;

		} else if (!base_layer_staged) {

			cstate->dim_layer[i].stage += SDE_STAGE_0;

		}

	}
@@ -4236,9 +4238,12 @@ static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc, 
			int sec_stage = cnt ? pstates[0].sde_pstate->stage :

						cstate->dim_layer[0].stage;



			if (!sde_kms->catalog->has_base_layer)

				sec_stage -= SDE_STAGE_0;



			if ((!cnt && !cstate->num_dim_layers) ||

				(sde_kms->catalog->sui_supported_blendstage

						!= (sec_stage - SDE_STAGE_0))) {

						!= sec_stage)) {

				SDE_ERROR(

				  "crtc%d: empty cnt%d/dim%d or bad stage%d\n",

					DRMID(crtc), cnt,
@@ -4424,7 +4429,7 @@ static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc, 
		/* check dim layer stage with every plane */

		for (i = 0; i < cstate->num_dim_layers; i++) {

			if (cstate->dim_layer[i].stage ==

					(pstates[*cnt].stage + SDE_STAGE_0)) {

					pstates[*cnt].stage) {

				SDE_ERROR(

					"plane:%d/dim_layer:%i-same stage:%d\n",

					plane->base.id, i,
@@ -4500,10 +4505,21 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state, 
{

	int rc = 0, i, z_pos;

	u32 zpos_cnt = 0;

	struct drm_crtc *crtc;

	struct sde_kms *kms;



	crtc = &sde_crtc->base;

	kms = _sde_crtc_get_kms(crtc);



	if (!kms || !kms->catalog) {

		SDE_ERROR("Invalid kms\n");

		return -EINVAL;

	}



	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);



	rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);

	rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt,

				kms->catalog->has_base_layer);

	if (rc)

		return rc;
@@ -4539,7 +4555,11 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state, 
			zpos_cnt++;

		}



		if (!kms->catalog->has_base_layer)

			pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;

		else

			pstates[i].sde_pstate->stage = z_pos;



		SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);

	}

	return rc;

msm/sde/sde_hw_catalog.c

+3 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ enum sde_prop { 
	PIPE_ORDER_VERSION,

	SEC_SID_MASK,

	SDE_LIMITS,

	BASE_LAYER,

	SDE_PROP_MAX,

};
@@ -489,6 +490,7 @@ static struct sde_prop_type sde_prop[] = { 
			PROP_TYPE_U32},

	{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},

	{SDE_LIMITS, "qcom,sde-limits", false, PROP_TYPE_NODE},

	{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},

};



static struct sde_prop_type sde_perf_prop[] = {
@@ -3418,6 +3420,7 @@ static int sde_top_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0);

	cfg->pipe_order_type = PROP_VALUE_ACCESS(prop_value,

		PIPE_ORDER_VERSION, 0);

	cfg->has_base_layer = PROP_VALUE_ACCESS(prop_value, BASE_LAYER, 0);



	rc = sde_limit_parse_dt(np, cfg);

	if (rc)

msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1275,6 +1275,7 @@ struct sde_limit_cfg { 
 * @has_qos_fl_nocalc  flag to indicate QoS fill level needs no calculation

 * @update_tcsr_disp_glitch  flag to enable HW workaround to avoid spurious

 *                            transactions during suspend

 * @has_base_layer     Supports staging layer as base layer

 * @sc_cfg: system cache configuration

 * @uidle_cfg		Settings for uidle feature

 * @sui_misr_supported  indicate if secure-ui-misr is supported
@@ -1336,6 +1337,7 @@ struct sde_mdss_cfg { 
	bool has_decimation;

	bool has_qos_fl_nocalc;

	bool update_tcsr_disp_glitch;

	bool has_base_layer;



	struct sde_sc_cfg sc_cfg;

msm/sde/sde_hw_ctl.c

+4 −2
Original line number Diff line number Diff line
@@ -790,8 +790,6 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 
	else

		pipes_per_stage = 1;



	mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */



	if (!stage_cfg)

		goto exit;
@@ -898,6 +896,10 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx, 
	}



exit:

	if ((!mixercfg && !mixercfg_ext && !mixercfg_ext2 && !mixercfg_ext3) ||

			(stage_cfg && !stage_cfg->stage[0][0]))

		mixercfg |= CTL_MIXER_BORDER_OUT;



	SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg);

	SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);

	SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);

msm/sde/sde_hw_lm.c

+3 −0
Original line number Diff line number Diff line
@@ -196,6 +196,9 @@ static void sde_hw_lm_setup_dim_layer(struct sde_hw_mixer *ctx, 
	int stage_off;

	u32 val = 0, alpha = 0;



	if (dim_layer->stage == SDE_STAGE_BASE)

		return;



	stage_off = _stage_offset(ctx, dim_layer->stage);

	if (stage_off < 0) {

		SDE_ERROR("invalid stage_off:%d for dim layer\n", stage_off);