Merge "dt-bindings: ice: Add DT binding entry for crypto drivers"

* QCEDEV (QTI Crypto Engine Device)

[Root level node]

Crypto Engine

============

Required properties:

  - compatible : should be "qcom,qcedev"

  - reg : should contain crypto, BAM register map.

  - reg-names : should contain the crypto and bam base register names.

  - interrupts : should contain crypto BAM interrupt.

  - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index.

  - qcom,ce-hw-instance : should contain crypto HW instance.

  - qcom,msm_bus,name: Should be "qcedev-noc"

  - qcom,msm_bus,num_cases: Depends on the use cases for bus scaling

  - qcom,msm_bus,active-only: Boolean flag for context of request (actve/dual)

  - qcom,msm_bus,num_paths: The paths for source and destination ports

  - qcom,msm_bus,vectors: Vectors for bus topology.

  - qcom,ce-device: Device number.

  - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.

Optional properties:

  - qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE.

  - qcom,ce-hw-key : optional, indicates if the hardware supports use of HW KEY.

  - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk.

  - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target. Default value is 1 if not specified.

  - qcom,smmu-s1-enable : Boolean flag to enable SMMU stage 1 translation.

  - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

  - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver.

[Second level nodes]

Context banks

=============

Required properties:

  - compatible : should be "qcom,qcedev,context-bank"

  - iommus : A phandle parsed by smmu driver. Number of entries will vary across targets.

Optional properties:

  - label - string describing iommu domain usage.

  - virtual-addr : start of virtual address pool.

  - virtual-size : size of virtual address pool.

Example:

	qcom,qcedev@fd440000 {

		compatible = "qcom,qcedev";

		reg = <0xfd440000 0x20000>,

			<0xfd444000 0x8000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 235 0>;

		qcom,bam-pipe-pair = <0>;

		qcom,ce-hw-instance = <1>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

                qcom,msm-bus,name = "qcedev-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<56 512 0 0>,

				<56 512 3936000 393600>,

		qcom,ce-opp-freq = <100000000>;

		qcom_cedev_ns_cb {

			compatible = "qcom,qcedev,context-bank";

			label = "ns_context";

			iommus = <&anoc2_smmu 0x1878>,

				<&anoc2_smmu 0x1879>,

				<&anoc2_smmu 0x187c>,

				<&anoc2_smmu 0x187f>;

			virtual-addr = <0x60000000>;

			virtual-size = <0x00200000>;

		};

	};

* QCOTA (Over The Air Crypto Device)

Required properties:

  - compatible : should be "qcom,qcota"

  - reg : should contain crypto, BAM register map.

  - reg-names : should contain the crypto and bam base register names.

  - interrupts : should contain crypto BAM interrupt.

  - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index.

  - qcom,ce-hw-instance : should contain crypto HW instance.

  - qcom,ce-device: Unique QCOTA device identifier. 0 for first

			instance, 1 for second instance, n-1 for n-th instance.

  - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.

Optional properties:

  - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk.

  - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target.Default value is 1 if not specified.

Example:

	qcom,qcota@fe140000 {

		compatible = "qcom,qcota";

		reg = <0xfe140000 0x20000>,

			<0xfe144000 0x8000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 111 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <2>;

		qcom,ce-device = <0>;

		qcom,ce-opp-freq = <100000000>;

	};

	qcom,qcota@fe0c0000 {

		compatible = "qcom,qcota";

		reg = <0xfe0c0000 0x20000>,

			<0xfe0c4000 0x8000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 113 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <4>;

		qcom,ce-device = <1>;

		qcom,ce-opp-freq = <100000000>;

	};

* QCRYPTO (QTI Crypto)

Required properties:

  - compatible : should be "qcom,qcrypto"

  - reg : should contain crypto, BAM register map.

  - reg-names : should contain the crypto and bam base register names.

  - interrupts : should contain crypto BAM interrupt.

  - qcom,bam-pipe-pair : should contain crypto BAM pipe pair index.

  - qcom,ce-hw-instance : should contain crypto HW instance.

  - qcom,msm_bus,name: Should be "qcrypto-noc"

  - qcom,msm_bus,num_cases: Depends on the use cases for bus scaling

  - qcom,msm_bus,active-only: Boolean flag for context of request (actve/dual)

  - qcom,msm_bus,num_paths: The paths for source and destination ports

  - qcom,ce-device: Device number. Device number is encoded with the following:

		bit 3-0   device type:	0 for full disk encryption(fde)

					1 for per file encrption(pfe)

		bit 7-4   unit number within the device type.

Optional properties:

  - qcom,ce-hw-shared : optional, indicates if the hardware is shared between EE.

  - qcom,ce-hw-key : optional, indicates if the hardware supports use of HW KEY.

  - qcom,use-sw-aes-cbc-ecb-ctr-algo : optional, indicates if use SW aes-cbc/ecb/ctr algorithm.

  - qcom,use-sw-aes-xts-algo : optional, indicates if use SW aes-xts algorithm.

  - qcom,use-sw-aead-algo : optional, indicates if use SW aead algorithm.

  - qcom,use-sw-ahash-algo : optional, indicates if use SW hash algorithm.

  - qcom,use-sw-hmac-algo : optional, indicates if use SW hmac algorithm.

  - qcom,use-sw-aes-ccm-algo : optional, indicates if use SW aes-ccm algorithm.

  - qcom,clk-mgmt-sus-res : optional, indicate if the ce clocks need to be disabled/enabled in suspend/resume function.

  - qcom,support-core-clk-only : optional, indicates if the HW supports single crypto core clk.

  - qcom,request-bw-before-clk : optional, indicates if the HW supports bandwidth requests prior to clock controls.

  - qcom,bsm-ee : optional, indicate the BAM EE value, changes from target to target.Default value is 1 if not specified.

  - qcom,ce-opp-freq: optional, indicates the CE operating frequency in Hz,

	changes from target to target. If not specified, by default the

	frequency is set as 100MHZ.

  - qcom,msm_bus,vectors: optional, indicates vectors for bus topology.

        This attribute is required for msm targets where bus scaling is

	required. For other targets such as fsm, they do not perform

	bus scaling. It is not required for those targets.

  - qcom,smmu-s1-enable : Boolean flag to bypass SMMU stage 1 translation.

  - iommus : A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device.

  - qcom,no-clock-support : indicates clocks are not handled by hlos crypto driver.

Example:

        qcom,qcrypto@fd444000 {

		compatible = "qcom,qcrypto";

		reg = <0xfd440000 0x20000>,

		      <0xfd444000 0x8000>;

		reg-names = "crypto-base","crypto-bam-base";

		interrupts = <0 235 0>;

		qcom,bam-pipe-pair = <1>;

		qcom,ce-hw-instance = <1>;

		qcom,ce-device = <0>;

		qcom,ce-hw-shared;

                qcom,msm-bus,name = "qcrypto-noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<56 512 0 0>,

				<56 512 3936000 393600>,

		qcom,ce-opp-freq = <100000000>;

	};