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Commit e6749c89 authored by Kuppuswamy Sathyanarayanan's avatar Kuppuswamy Sathyanarayanan Committed by Andy Shevchenko
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platform/x86: intel_pmc_ipc: fix gcr offset 



According to Broxton APL spec, PMC MIMO resources for Global Control
Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
region base address from IPC base address and its current value of
0x1008 is incorrect because it points to location for PMC_CFG register
and not the GCR base address itself.

GCR Base = IPC1 Base + 0x1000.

This patch fixes this offset issue.

Signed-off-by: default avatarKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
parent 9216e0dc

drivers/platform/x86/intel_pmc_ipc.c

+1 −1
Original line number Diff line number Diff line
@@ -82,7 +82,7 @@ 
/* exported resources from IFWI */

#define PLAT_RESOURCE_IPC_INDEX		0

#define PLAT_RESOURCE_IPC_SIZE		0x1000

#define PLAT_RESOURCE_GCR_OFFSET	0x1008

#define PLAT_RESOURCE_GCR_OFFSET	0x1000

#define PLAT_RESOURCE_GCR_SIZE		0x1000

#define PLAT_RESOURCE_BIOS_DATA_INDEX	1

#define PLAT_RESOURCE_BIOS_IFACE_INDEX	2