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Commit e6698305 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:
 "This is the main pull request for 3.17.  It contains:

   - misc Cavium Octeon, BCM47xx, BCM63xx and Alchemy  updates
   - MIPS ptrace updates and cleanups
   - various fixes that will also go to -stable
   - a number of cleanups and small non-critical fixes.
   - NUMA support for the Loongson 3.
   - more support for MSA
   - support for MAAR
   - various FP enhancements and fixes"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  MIPS: jz4740: remove unnecessary null test before debugfs_remove
  MIPS: Octeon: remove unnecessary null test before debugfs_remove_recursive
  MIPS: ZBOOT: implement stack protector in compressed boot phase
  MIPS: mipsreg: remove duplicate MIPS_CONF4_FTLBSETS_SHIFT
  MIPS: Bonito64: remove a duplicate define
  MIPS: Malta: initialise MAARs
  MIPS: Initialise MAARs
  MIPS: detect presence of MAARs
  MIPS: define MAAR register accessors & bits
  MIPS: mark MSA experimental
  MIPS: Don't build MSA support unless it can be used
  MIPS: consistently clear MSA flags when starting & copying threads
  MIPS: 16 byte align MSA vector context
  MIPS: disable preemption whilst initialising MSA
  MIPS: ensure MSA gets disabled during boot
  MIPS: fix read_msa_* & write_msa_* functions on non-MSA toolchains
  MIPS: fix MSA context for tasks which don't use FP first
  MIPS: init upper 64b of vector registers when MSA is first used
  MIPS: save/disable MSA in lose_fpu
  MIPS: preserve scalar FP CSR when switching vector context
  ...
parents ebb067d2 475d5928

Documentation/kernel-parameters.txt

+6 −0
Original line number Diff line number Diff line
@@ -571,6 +571,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			trust validation.

			format: { id:<keyid> | builtin }



	cca=		[MIPS] Override the kernel pages' cache coherency

			algorithm.  Accepted values range from 0 to 7

			inclusive. See arch/mips/include/asm/pgtable-bits.h

			for platform specific values (SB1, Loongson3 and

			others).



	ccw_timeout_log [S390]

			See Documentation/s390/CommonIO for details.

arch/mips/Kconfig

+7 −2
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ config MIPS_ALCHEMY 
	select SYS_SUPPORTS_APM_EMULATION

	select ARCH_REQUIRE_GPIOLIB

	select SYS_SUPPORTS_ZBOOT

	select COMMON_CLK



config AR7

	bool "Texas Instruments AR7"
@@ -129,6 +130,8 @@ config BCM47XX 
	select SYS_SUPPORTS_MIPS16

	select SYS_HAS_EARLY_PRINTK

	select USE_GENERIC_EARLY_PRINTK_8250

	select GPIOLIB

	select LEDS_GPIO_REGISTER

	help

	 Support for BCM47XX based boards
@@ -137,6 +140,7 @@ config BCM63XX 
	select BOOT_RAW

	select CEVT_R4K

	select CSRC_R4K

	select SYNC_R4K

	select DMA_NONCOHERENT

	select IRQ_CPU

	select SYS_SUPPORTS_32BIT_KERNEL
@@ -2056,6 +2060,7 @@ config MIPS_CPS 
	  support is unavailable.



config MIPS_CPS_PM

	select MIPS_CPC

	bool



config MIPS_GIC_IPI
@@ -2109,9 +2114,9 @@ config CPU_MICROMIPS 
	  microMIPS ISA



config CPU_HAS_MSA

	bool "Support for the MIPS SIMD Architecture"

	bool "Support for the MIPS SIMD Architecture (EXPERIMENTAL)"

	depends on CPU_SUPPORTS_MSA

	default y

	depends on 64BIT || MIPS_O32_FP64_SUPPORT

	help

	  MIPS SIMD Architecture (MSA) introduces 128 bit wide vector registers

	  and a set of SIMD instructions to operate on them. When this option

arch/mips/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -151,8 +151,10 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ 
			-Wa,--trap

cflags-$(CONFIG_CPU_RM7000)	+= $(call cc-option,-march=rm7000,-march=r5000) \

			-Wa,--trap

cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1 -mno-mdmx -mno-mips3d,-march=r5000) \

cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-march=sb1,-march=r5000) \

			-Wa,--trap

cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mdmx)

cflags-$(CONFIG_CPU_SB1)	+= $(call cc-option,-mno-mips3d)

cflags-$(CONFIG_CPU_R8000)	+= -march=r8000 -Wa,--trap

cflags-$(CONFIG_CPU_R10000)	+= $(call cc-option,-march=r10000,-march=r8000) \

			-Wa,--trap

arch/mips/alchemy/board-mtx1.c

+2 −2
Original line number Diff line number Diff line
@@ -85,10 +85,10 @@ void __init board_setup(void) 
#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */



	/* Initialize sys_pinfunc */

	au_writel(SYS_PF_NI2, SYS_PINFUNC);

	alchemy_wrsys(SYS_PF_NI2, AU1000_SYS_PINFUNC);



	/* Initialize GPIO */

	au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);

	alchemy_wrsys(~0, AU1000_SYS_TRIOUTCLR);

	alchemy_gpio_direction_output(0, 0);	/* Disable M66EN (PCI 66MHz) */

	alchemy_gpio_direction_output(3, 1);	/* Disable PCI CLKRUN# */

	alchemy_gpio_direction_output(1, 1);	/* Enable EXT_IO3 */

arch/mips/alchemy/board-xxs1500.c

+2 −2
Original line number Diff line number Diff line
@@ -87,9 +87,9 @@ void __init board_setup(void) 
	alchemy_gpio2_enable();



	/* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */

	pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;

	pin_func  = alchemy_rdsys(AU1000_SYS_PINFUNC) & ~SYS_PF_UR3;

	pin_func |= SYS_PF_UR3;

	au_writel(pin_func, SYS_PINFUNC);

	alchemy_wrsys(pin_func, AU1000_SYS_PINFUNC);



	/* Enable UART */

	alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);