Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e65a139d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-for-v4.14-rc8' of git://people.freedesktop.org/~airlied/linux

Pull drm fixes from Dave Airlie:

 - one nouveau regression fix

 - some amdgpu fixes for stable to fix hangs on some harvested Polaris
   GPUs

 - a set of KASAN and regression fixes for i915, their CI system seems
   to be working pretty well now.

* tag 'drm-fixes-for-v4.14-rc8' of git://people.freedesktop.org/~airlied/linux:
  drm/amdgpu: allow harvesting check for Polaris VCE
  drm/amdgpu: return -ENOENT from uvd 6.0 early init for harvesting
  drm/i915: Check incoming alignment for unfenced buffers (on i915gm)
  drm/nouveau/kms/nv50: use the correct state for base channel notifier setup
  drm/i915: Hold rcu_read_lock when iterating over the radixtree (vma idr)
  drm/i915: Hold rcu_read_lock when iterating over the radixtree (objects)
  drm/i915/edp: read edp display control registers unconditionally
  drm/i915: Do not rely on wm preservation for ILK watermarks
  drm/i915: Cancel the modeset retry work during modeset cleanup
parents 7ba3ebff 9cc06965
Loading
Loading
Loading
Loading
+4 −0
Original line number Diff line number Diff line
@@ -93,6 +93,10 @@ static int uvd_v6_0_early_init(void *handle)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	if (!(adev->flags & AMD_IS_APU) &&
	    (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK))
		return -ENOENT;

	uvd_v6_0_set_ring_funcs(adev);
	uvd_v6_0_set_irq_funcs(adev);

+6 −6
Original line number Diff line number Diff line
@@ -365,15 +365,10 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
{
	u32 tmp;

	/* Fiji, Stoney, Polaris10, Polaris11, Polaris12 are single pipe */
	if ((adev->asic_type == CHIP_FIJI) ||
	    (adev->asic_type == CHIP_STONEY) ||
	    (adev->asic_type == CHIP_POLARIS10) ||
	    (adev->asic_type == CHIP_POLARIS11) ||
	    (adev->asic_type == CHIP_POLARIS12))
	    (adev->asic_type == CHIP_STONEY))
		return AMDGPU_VCE_HARVEST_VCE1;

	/* Tonga and CZ are dual or single pipe */
	if (adev->flags & AMD_IS_APU)
		tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
		       VCE_HARVEST_FUSE_MACRO__MASK) >>
@@ -391,6 +386,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
	case 3:
		return AMDGPU_VCE_HARVEST_VCE0 | AMDGPU_VCE_HARVEST_VCE1;
	default:
		if ((adev->asic_type == CHIP_POLARIS10) ||
		    (adev->asic_type == CHIP_POLARIS11) ||
		    (adev->asic_type == CHIP_POLARIS12))
			return AMDGPU_VCE_HARVEST_VCE1;

		return 0;
	}
}
+2 −0
Original line number Diff line number Diff line
@@ -2214,8 +2214,10 @@ static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)
	struct radix_tree_iter iter;
	void __rcu **slot;

	rcu_read_lock();
	radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)
		radix_tree_delete(&obj->mm.get_page.radix, iter.index);
	rcu_read_unlock();
}

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
+2 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ static void lut_close(struct i915_gem_context *ctx)
		kmem_cache_free(ctx->i915->luts, lut);
	}

	rcu_read_lock();
	radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
		struct i915_vma *vma = rcu_dereference_raw(*slot);
		struct drm_i915_gem_object *obj = vma->obj;
@@ -115,6 +116,7 @@ static void lut_close(struct i915_gem_context *ctx)

		__i915_gem_object_release_unless_active(obj);
	}
	rcu_read_unlock();
}

static void i915_gem_context_free(struct i915_gem_context *ctx)
+4 −0
Original line number Diff line number Diff line
@@ -337,6 +337,10 @@ eb_vma_misplaced(const struct drm_i915_gem_exec_object2 *entry,
	    (vma->node.start + vma->node.size - 1) >> 32)
		return true;

	if (flags & __EXEC_OBJECT_NEEDS_MAP &&
	    !i915_vma_is_map_and_fenceable(vma))
		return true;

	return false;
}

Loading