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Commit e598e6eb authored by Kedareswara rao Appana's avatar Kedareswara rao Appana Committed by Vinod Koul
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dmaengine: xilinx: Fix race condition in axi dma cyclic dma mode 



In cyclic DMA mode need to link the tail bd segment
with the head bd segment to process bd's in cyclic.

Current driver is doing this only for tx channel
needs to update the same for rx channel case also.

This patch fixes the same.

Signed-off-by: default avatarKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent b0cc417c

drivers/dma/xilinx/xilinx_dma.c

+5 −4
Original line number Diff line number Diff line
@@ -1895,14 +1895,15 @@ static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 
	reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK;

	dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);



	/* For the last DMA_MEM_TO_DEV transfer, set EOP */

	if (direction == DMA_MEM_TO_DEV) {

		head_segment->hw.control |= XILINX_DMA_BD_SOP;

	segment = list_last_entry(&desc->segments,

				  struct xilinx_axidma_tx_segment,

				  node);

		segment->hw.control |= XILINX_DMA_BD_EOP;

	segment->hw.next_desc = (u32) head_segment->phys;



	/* For the last DMA_MEM_TO_DEV transfer, set EOP */

	if (direction == DMA_MEM_TO_DEV) {

		head_segment->hw.control |= XILINX_DMA_BD_SOP;

		segment->hw.control |= XILINX_DMA_BD_EOP;

	}



	return &desc->async_tx;