Loading arch/sparc/include/asm/cpudata_64.h +1 −1 Original line number Diff line number Diff line Loading @@ -17,7 +17,7 @@ typedef struct { /* Dcache line 1 */ unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ unsigned int __pad0; unsigned int __nmi_count; unsigned long clock_tick; /* %tick's per second */ unsigned long __pad; unsigned int __pad1; Loading arch/sparc/include/asm/irq_64.h +1 −3 Original line number Diff line number Diff line Loading @@ -66,9 +66,6 @@ extern void virt_irq_free(unsigned int virt_irq); extern void __init init_IRQ(void); extern void fixup_irqs(void); extern int register_perfctr_intr(void (*handler)(struct pt_regs *)); extern void release_perfctr_intr(void (*handler)(struct pt_regs *)); static inline void set_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%set_softint" Loading Loading @@ -98,5 +95,6 @@ void __trigger_all_cpu_backtrace(void); extern void *hardirq_stack[NR_CPUS]; extern void *softirq_stack[NR_CPUS]; #define __ARCH_HAS_DO_SOFTIRQ #define ARCH_HAS_NMI_WATCHDOG #endif arch/sparc/include/asm/kdebug_64.h +2 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,8 @@ enum die_val { DIE_TRAP, DIE_TRAP_TL1, DIE_CALL, DIE_NMI, DIE_NMIWATCHDOG, }; #endif arch/sparc/include/asm/nmi.h 0 → 100644 +10 −0 Original line number Diff line number Diff line #ifndef __NMI_H #define __NMI_H extern int __init nmi_init(void); extern void perfctr_irq(int irq, struct pt_regs *regs); extern void nmi_adjust_hz(unsigned int new_hz); extern int nmi_usable; #endif /* __NMI_H */ arch/sparc/include/asm/pcr.h +16 −0 Original line number Diff line number Diff line Loading @@ -27,4 +27,20 @@ extern void schedule_deferred_pcr_work(void); #define PCR_N2_SL1_SHIFT 27 #define PCR_N2_OV1 0x80000000 extern unsigned int picl_shift; /* In order to commonize as much of the implementation as * possible, we use PICH as our counter. Mostly this is * to accomodate Niagara-1 which can only count insn cycles * in PICH. */ static inline u64 picl_value(unsigned int nmi_hz) { u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift); return ((u64)((0 - delta) & 0xffffffff)) << 32; } extern u64 pcr_enable; #endif /* __PCR_H */ Loading
arch/sparc/include/asm/cpudata_64.h +1 −1 Original line number Diff line number Diff line Loading @@ -17,7 +17,7 @@ typedef struct { /* Dcache line 1 */ unsigned int __softirq_pending; /* must be 1st, see rtrap.S */ unsigned int __pad0; unsigned int __nmi_count; unsigned long clock_tick; /* %tick's per second */ unsigned long __pad; unsigned int __pad1; Loading
arch/sparc/include/asm/irq_64.h +1 −3 Original line number Diff line number Diff line Loading @@ -66,9 +66,6 @@ extern void virt_irq_free(unsigned int virt_irq); extern void __init init_IRQ(void); extern void fixup_irqs(void); extern int register_perfctr_intr(void (*handler)(struct pt_regs *)); extern void release_perfctr_intr(void (*handler)(struct pt_regs *)); static inline void set_softint(unsigned long bits) { __asm__ __volatile__("wr %0, 0x0, %%set_softint" Loading Loading @@ -98,5 +95,6 @@ void __trigger_all_cpu_backtrace(void); extern void *hardirq_stack[NR_CPUS]; extern void *softirq_stack[NR_CPUS]; #define __ARCH_HAS_DO_SOFTIRQ #define ARCH_HAS_NMI_WATCHDOG #endif
arch/sparc/include/asm/kdebug_64.h +2 −0 Original line number Diff line number Diff line Loading @@ -14,6 +14,8 @@ enum die_val { DIE_TRAP, DIE_TRAP_TL1, DIE_CALL, DIE_NMI, DIE_NMIWATCHDOG, }; #endif
arch/sparc/include/asm/nmi.h 0 → 100644 +10 −0 Original line number Diff line number Diff line #ifndef __NMI_H #define __NMI_H extern int __init nmi_init(void); extern void perfctr_irq(int irq, struct pt_regs *regs); extern void nmi_adjust_hz(unsigned int new_hz); extern int nmi_usable; #endif /* __NMI_H */
arch/sparc/include/asm/pcr.h +16 −0 Original line number Diff line number Diff line Loading @@ -27,4 +27,20 @@ extern void schedule_deferred_pcr_work(void); #define PCR_N2_SL1_SHIFT 27 #define PCR_N2_OV1 0x80000000 extern unsigned int picl_shift; /* In order to commonize as much of the implementation as * possible, we use PICH as our counter. Mostly this is * to accomodate Niagara-1 which can only count insn cycles * in PICH. */ static inline u64 picl_value(unsigned int nmi_hz) { u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift); return ((u64)((0 - delta) & 0xffffffff)) << 32; } extern u64 pcr_enable; #endif /* __PCR_H */