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Commit e50a0d4a authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Greg Kroah-Hartman
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PCI: Add #defines for Enter Compliance, Transmit Margin 

[ Upstream commit bbdb2f5ecdf1e66b2f09710134db3c2e5c43a958 ]

Add definitions for the Enter Compliance and Transmit Margin fields of the
PCIe Link Control 2 register.

Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent eac3517c

include/uapi/linux/pci_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -671,6 +671,8 @@ 
#define  PCI_EXP_LNKCTL2_TLS_8_0GT	0x0003 /* Supported Speed 8GT/s */

#define  PCI_EXP_LNKCTL2_TLS_16_0GT	0x0004 /* Supported Speed 16GT/s */

#define  PCI_EXP_LNKCTL2_TLS_32_0GT	0x0005 /* Supported Speed 32GT/s */

#define  PCI_EXP_LNKCTL2_ENTER_COMP	0x0010 /* Enter Compliance */

#define  PCI_EXP_LNKCTL2_TX_MARGIN	0x0380 /* Transmit Margin */

#define PCI_EXP_LNKSTA2		50	/* Link Status 2 */

#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2	52	/* v2 endpoints with link end here */

#define PCI_EXP_SLTCAP2		52	/* Slot Capabilities 2 */