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Commit e4ffc83d authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915/cnl: WaRsUseTimeoutMode 



Apparently RC6 residency is lower than expected
with EI mode for most of the cases on CNL A0, B0 and C0.

This Wa doesn't solve our lower residency, but I
believe it is better to have it since EI is not
expected to work by HW engineers anyways.

Cc: David Weinehall <david.weinehall@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDavid Weinehall <david.weinehall@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170822235828.18322-1-rodrigo.vivi@intel.com
parent 543d5e0e

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -3077,6 +3077,7 @@ intel_info(const struct drm_i915_private *dev_priv) 




#define CNL_REVID_A0		0x0

#define CNL_REVID_A0		0x0

#define CNL_REVID_B0		0x1

#define CNL_REVID_B0		0x1

#define CNL_REVID_C0		0x2





#define IS_CNL_REVID(p, since, until) \

#define IS_CNL_REVID(p, since, until) \

	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

drivers/gpu/drm/i915/intel_pm.c

+9 −2
Original line number Original line Diff line number Diff line
@@ -6591,7 +6591,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) 
{

{

	struct intel_engine_cs *engine;

	struct intel_engine_cs *engine;

	enum intel_engine_id id;

	enum intel_engine_id id;

	uint32_t rc6_mask = 0;

	u32 rc6_mode, rc6_mask = 0;





	/* 1a: Software RC state - RC0 */

	/* 1a: Software RC state - RC0 */

	I915_WRITE(GEN6_RC_STATE, 0);

	I915_WRITE(GEN6_RC_STATE, 0);
@@ -6629,8 +6629,15 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) 
		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;

		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;

	DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));

	DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));

	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */

	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */



	/* WaRsUseTimeoutMode:cnl (pre-prod) */

	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))

		rc6_mode = GEN7_RC_CTL_TO_MODE;

	else

		rc6_mode = GEN6_RC_CTL_EI_MODE(1);



	I915_WRITE(GEN6_RC_CONTROL,

	I915_WRITE(GEN6_RC_CONTROL,

		   GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);

		   GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);





	/*

	/*

	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.

	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.