Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e4517e94 authored by Carter Cooper's avatar Carter Cooper Committed by Puranam V G Tejaswi
Browse files

msm: kgsl: Add handler for GPC interrupt on A6xx GPU 



Add the interrupt handler to cause a snapshot when the
GPC interrupt is received for A6xx.

Change-Id: I6eabde0f2bdfc3997bf380055246c2cbdada7cdf
Signed-off-by: default avatarCarter Cooper <ccooper@codeaurora.org>
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
Signed-off-by: default avatarRajesh Kemisetti <rajeshk@codeaurora.org>
parent 23ef43f2

drivers/gpu/msm/adreno_a5xx.c

+4 −4
Original line number Diff line number Diff line
@@ -2846,11 +2846,11 @@ static void a5xx_gpmu_int_callback(struct adreno_device *adreno_dev, int bit) 
}



/*

 * a5x_gpc_err_int_callback() - Isr for GPC error interrupts

 * a5xx_gpc_err_int_callback() - Isr for GPC error interrupts

 * @adreno_dev: Pointer to device

 * @bit: Interrupt bit

 */

void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)

static void a5xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -2860,7 +2860,7 @@ void a5x_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit) 
	 * with help of register dump.

	 */



	dev_crit(device->dev, "RBBM: GPC error\n");

	dev_crit_ratelimited(device->dev, "RBBM: GPC error\n");

	adreno_irqctrl(adreno_dev, 0);



	/* Trigger a fault in the dispatcher - this will effect a restart */
@@ -2898,7 +2898,7 @@ static struct adreno_irq_funcs a5xx_irq_funcs[32] = { 
	ADRENO_IRQ_CALLBACK(a5xx_err_callback),

	/* 6 - RBBM_ATB_ASYNC_OVERFLOW */

	ADRENO_IRQ_CALLBACK(a5xx_err_callback),

	ADRENO_IRQ_CALLBACK(a5x_gpc_err_int_callback), /* 7 - GPC_ERR */

	ADRENO_IRQ_CALLBACK(a5xx_gpc_err_int_callback), /* 7 - GPC_ERR */

	ADRENO_IRQ_CALLBACK(a5xx_preempt_callback),/* 8 - CP_SW */

	ADRENO_IRQ_CALLBACK(a5xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */

	/* 10 - CP_CCU_FLUSH_DEPTH_TS */

drivers/gpu/msm/adreno_a6xx.c

+24 −1
Original line number Diff line number Diff line
@@ -1392,6 +1392,29 @@ static void a6xx_cp_callback(struct adreno_device *adreno_dev, int bit) 
	adreno_dispatcher_schedule(device);

}



/*

 * a6xx_gpc_err_int_callback() - Isr for GPC error interrupts

 * @adreno_dev: Pointer to device

 * @bit: Interrupt bit

 */

static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);



	/*

	 * GPC error is typically the result of mistake SW programming.

	 * Force GPU fault for this interrupt so that we can debug it

	 * with help of register dump.

	 */



	dev_crit_ratelimited(device->dev, "RBBM: GPC error\n");

	adreno_irqctrl(adreno_dev, 0);



	/* Trigger a fault in the dispatcher - this will effect a restart */

	adreno_set_gpu_fault(adreno_dev, ADRENO_SOFT_FAULT);

	adreno_dispatcher_schedule(device);

}



#define A6XX_INT_MASK \

	((1 << A6XX_INT_CP_AHB_ERROR) |			\

	 (1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) |	\
@@ -1417,7 +1440,7 @@ static struct adreno_irq_funcs a6xx_irq_funcs[32] = { 
	ADRENO_IRQ_CALLBACK(NULL), /* 5 - UNUSED */

	/* 6 - RBBM_ATB_ASYNC_OVERFLOW */

	ADRENO_IRQ_CALLBACK(a6xx_err_callback),

	ADRENO_IRQ_CALLBACK(NULL), /* 7 - GPC_ERR */

	ADRENO_IRQ_CALLBACK(a6xx_gpc_err_int_callback), /* 7 - GPC_ERR */

	ADRENO_IRQ_CALLBACK(a6xx_preemption_callback),/* 8 - CP_SW */

	ADRENO_IRQ_CALLBACK(a6xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */

	ADRENO_IRQ_CALLBACK(NULL),  /* 10 - CP_CCU_FLUSH_DEPTH_TS */