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Commit e41a6f6d authored by Stewart Robertson's avatar Stewart Robertson Committed by Greg Kroah-Hartman
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Staging: comedi: fix coding style issues in ni_labpc.c 



This is a patch to the ni_labpc.c file that fixes the brace warnings and
comments over 80 characters found by the checkpatch.pl tool. Some code
still goes over 80 characters because I didn't know what to do with it.

Signed-off-by: default avatarStewart Robertson <stewart_r@aliencamel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent af71b816

drivers/staging/comedi/drivers/ni_labpc.c

+145 −86
Original line number Diff line number Diff line
@@ -90,8 +90,10 @@ NI manuals: 


#define DRV_NAME "ni_labpc"



#define LABPC_SIZE           32	/*  size of io region used by board */

#define LABPC_TIMER_BASE            500	/*  2 MHz master clock */

/* size of io region used by board */

#define LABPC_SIZE           32

/* 2 MHz master clock */

#define LABPC_TIMER_BASE            500



/* Registers for the lab-pc+ */
@@ -99,69 +101,110 @@ NI manuals: 
#define COMMAND1_REG	0x0

#define   ADC_GAIN_MASK	(0x7 << 4)

#define   ADC_CHAN_BITS(x)	((x) & 0x7)

#define   ADC_SCAN_EN_BIT	0x80	/*  enables multi channel scans */

/* enables multi channel scans */

#define   ADC_SCAN_EN_BIT	0x80

#define COMMAND2_REG	0x1

#define   PRETRIG_BIT	0x1	/*  enable pretriggering (used in conjunction with SWTRIG) */

#define   HWTRIG_BIT	0x2	/*  enable paced conversions on external trigger */

#define   SWTRIG_BIT	0x4	/*  enable paced conversions */

#define   CASCADE_BIT	0x8	/*  use two cascaded counters for pacing */

/* enable pretriggering (used in conjunction with SWTRIG) */

#define   PRETRIG_BIT	0x1

/* enable paced conversions on external trigger */

#define   HWTRIG_BIT	0x2

/* enable paced conversions */

#define   SWTRIG_BIT	0x4

/* use two cascaded counters for pacing */

#define   CASCADE_BIT	0x8

#define   DAC_PACED_BIT(channel)	(0x40 << ((channel) & 0x1))

#define COMMAND3_REG	0x2

#define   DMA_EN_BIT	0x1	/*  enable dma transfers */

#define   DIO_INTR_EN_BIT	0x2	/*  enable interrupts for 8255 */

#define   DMATC_INTR_EN_BIT	0x4	/*  enable dma terminal count interrupt */

#define   TIMER_INTR_EN_BIT	0x8	/*  enable timer interrupt */

#define   ERR_INTR_EN_BIT	0x10	/*  enable error interrupt */

#define   ADC_FNE_INTR_EN_BIT	0x20	/*  enable fifo not empty interrupt */

/* enable dma transfers */

#define   DMA_EN_BIT	0x1

/* enable interrupts for 8255 */

#define   DIO_INTR_EN_BIT	0x2

/* enable dma terminal count interrupt */

#define   DMATC_INTR_EN_BIT	0x4

/* enable timer interrupt */

#define   TIMER_INTR_EN_BIT	0x8

/* enable error interrupt */

#define   ERR_INTR_EN_BIT	0x10

/* enable fifo not empty interrupt */

#define   ADC_FNE_INTR_EN_BIT	0x20

#define ADC_CONVERT_REG	0x3

#define DAC_LSB_REG(channel)	(0x4 + 2 * ((channel) & 0x1))

#define DAC_MSB_REG(channel)	(0x5 + 2 * ((channel) & 0x1))

#define ADC_CLEAR_REG	0x8

#define DMATC_CLEAR_REG	0xa

#define TIMER_CLEAR_REG	0xc

#define COMMAND6_REG	0xe	/*  1200 boards only */

#define   ADC_COMMON_BIT	0x1	/*  select ground or common-mode reference */

#define   ADC_UNIP_BIT	0x2	/*  adc unipolar */

#define   DAC_UNIP_BIT(channel)	(0x4 << ((channel) & 0x1))	/*  dac unipolar */

#define   ADC_FHF_INTR_EN_BIT	0x20	/*  enable fifo half full interrupt */

#define   A1_INTR_EN_BIT	0x40	/*  enable interrupt on end of hardware count */

#define   ADC_SCAN_UP_BIT 0x80	/*  scan up from channel zero instead of down to zero */

/* 1200 boards only */

#define COMMAND6_REG	0xe

/* select ground or common-mode reference */

#define   ADC_COMMON_BIT	0x1

/*  adc unipolar */

#define   ADC_UNIP_BIT	0x2

/*  dac unipolar */

#define   DAC_UNIP_BIT(channel)	(0x4 << ((channel) & 0x1))

/* enable fifo half full interrupt */

#define   ADC_FHF_INTR_EN_BIT	0x20

/* enable interrupt on end of hardware count */

#define   A1_INTR_EN_BIT	0x40

/* scan up from channel zero instead of down to zero */

#define   ADC_SCAN_UP_BIT 0x80

#define COMMAND4_REG	0xf

#define   INTERVAL_SCAN_EN_BIT	0x1	/*  enables 'interval' scanning */

#define   EXT_SCAN_EN_BIT	0x2	/*  enables external signal on counter b1 output to trigger scan */

#define   EXT_CONVERT_OUT_BIT	0x4	/*  chooses direction (output or input) for EXTCONV* line */

#define   ADC_DIFF_BIT	0x8	/*  chooses differential inputs for adc (in conjunction with board jumper) */

/* enables 'interval' scanning */

#define   INTERVAL_SCAN_EN_BIT	0x1

/* enables external signal on counter b1 output to trigger scan */

#define   EXT_SCAN_EN_BIT	0x2

/* chooses direction (output or input) for EXTCONV* line */

#define   EXT_CONVERT_OUT_BIT	0x4

/* chooses differential inputs for adc (in conjunction with board jumper) */

#define   ADC_DIFF_BIT	0x8

#define   EXT_CONVERT_DISABLE_BIT	0x10

#define COMMAND5_REG	0x1c	/*  1200 boards only, calibration stuff */

#define   EEPROM_WRITE_UNPROTECT_BIT	0x4	/*  enable eeprom for write */

#define   DITHER_EN_BIT	0x8	/*  enable dithering */

#define   CALDAC_LOAD_BIT	0x10	/*  load calibration dac */

#define   SCLOCK_BIT	0x20	/*  serial clock - rising edge writes, falling edge reads */

#define   SDATA_BIT	0x40	/*  serial data bit for writing to eeprom or calibration dacs */

#define   EEPROM_EN_BIT	0x80	/*  enable eeprom for read/write */

/* 1200 boards only, calibration stuff */

#define COMMAND5_REG	0x1c

/* enable eeprom for write */

#define   EEPROM_WRITE_UNPROTECT_BIT	0x4

/* enable dithering */

#define   DITHER_EN_BIT	0x8

/* load calibration dac */

#define   CALDAC_LOAD_BIT	0x10

/* serial clock - rising edge writes, falling edge reads */

#define   SCLOCK_BIT	0x20

/* serial data bit for writing to eeprom or calibration dacs */

#define   SDATA_BIT	0x40

/* enable eeprom for read/write */

#define   EEPROM_EN_BIT	0x80

#define INTERVAL_COUNT_REG	0x1e

#define INTERVAL_LOAD_REG	0x1f

#define   INTERVAL_LOAD_BITS	0x1



/* read-only registers */

#define STATUS1_REG	0x0

#define   DATA_AVAIL_BIT	0x1	/*  data is available in fifo */

#define   OVERRUN_BIT	0x2	/*  overrun has occurred */

#define   OVERFLOW_BIT	0x4	/*  fifo overflow */

#define   TIMER_BIT	0x8	/*  timer interrupt has occured */

#define   DMATC_BIT	0x10	/*  dma terminal count has occured */

#define   EXT_TRIG_BIT	0x40	/*  external trigger has occured */

#define STATUS2_REG	0x1d	/*  1200 boards only */

#define   EEPROM_OUT_BIT	0x1	/*  programmable eeprom serial output */

#define   A1_TC_BIT	0x2	/*  counter A1 terminal count */

#define   FNHF_BIT	0x4	/*  fifo not half full */

/* data is available in fifo */

#define   DATA_AVAIL_BIT	0x1

/* overrun has occurred */

#define   OVERRUN_BIT	0x2

/* fifo overflow */

#define   OVERFLOW_BIT	0x4

/* timer interrupt has occured */

#define   TIMER_BIT	0x8

/* dma terminal count has occured */

#define   DMATC_BIT	0x10

/* external trigger has occured */

#define   EXT_TRIG_BIT	0x40

/* 1200 boards only */

#define STATUS2_REG	0x1d

/* programmable eeprom serial output */

#define   EEPROM_OUT_BIT	0x1

/* counter A1 terminal count */

#define   A1_TC_BIT	0x2

/* fifo not half full */

#define   FNHF_BIT	0x4

#define ADC_FIFO_REG	0xa



#define DIO_BASE_REG	0x10

#define COUNTER_A_BASE_REG	0x14

#define COUNTER_A_CONTROL_REG	(COUNTER_A_BASE_REG + 0x3)

#define   INIT_A0_BITS	0x14	/*  check modes put conversion pacer output in harmless state (a0 mode 2) */

#define   INIT_A1_BITS	0x70	/*  put hardware conversion counter output in harmless state (a1 mode 0) */

/* check modes put conversion pacer output in harmless state (a0 mode 2) */

#define   INIT_A0_BITS	0x14

/* put hardware conversion counter output in harmless state (a1 mode 0) */

#define   INIT_A1_BITS	0x70

#define COUNTER_B_BASE_REG	0x18



static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
@@ -436,8 +479,10 @@ static const struct labpc_board_struct labpc_boards[] = { 
 */

#define thisboard ((struct labpc_board_struct *)dev->board_ptr)



static const int dma_buffer_size = 0xff00;	/*  size in bytes of dma buffer */

static const int sample_size = 2;	/*  2 bytes per sample */

/* size in bytes of dma buffer */

static const int dma_buffer_size = 0xff00;

/* 2 bytes per sample */

static const int sample_size = 2;



#define devpriv ((struct labpc_private *)dev->private)
@@ -1182,7 +1227,8 @@ static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||

	    labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {

		devpriv->command1_bits |= ADC_SCAN_EN_BIT;

		/* need a brief delay before enabling scan, or scan list will get screwed when you switch

		/* need a brief delay before enabling scan, or scan

		 * list will get screwed when you switch

		 * between scan up to scan down mode - dunno why */

		udelay(1);

		devpriv->write_byte(devpriv->command1_bits,
@@ -1719,13 +1765,21 @@ static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) 
/* figures out what counter values to use based on command */

static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)

{

	const int max_counter_value = 0x10000;	/*  max value for 16 bit counter in mode 2 */

	const int min_counter_value = 2;	/*  min value for 16 bit counter in mode 2 */

	/* max value for 16 bit counter in mode 2 */

	const int max_counter_value = 0x10000;

	/* min value for 16 bit counter in mode 2 */

	const int min_counter_value = 2;

	unsigned int base_period;



	/*  if both convert and scan triggers are TRIG_TIMER, then they both rely on counter b0 */

	/*

	 * if both convert and scan triggers are TRIG_TIMER, then they

	 * both rely on counter b0

	 */

	if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {

		/*  pick the lowest b0 divisor value we can (for maximum input clock speed on convert and scan counters) */

		/*

		 * pick the lowest b0 divisor value we can (for maximum input

		 * clock speed on convert and scan counters)

		 */

		devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /

		    (LABPC_TIMER_BASE * max_counter_value) + 1;

		if (devpriv->divisor_b0 < min_counter_value)
@@ -1775,7 +1829,10 @@ static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) 
					    base_period * devpriv->divisor_a0);

		labpc_set_ai_scan_period(cmd,

					 base_period * devpriv->divisor_b1);

		/*  if only one TRIG_TIMER is used, we can employ the generic cascaded timing functions */

		/*

		 * if only one TRIG_TIMER is used, we can employ the generic

		 * cascaded timing functions

		 */

	} else if (labpc_ai_scan_period(cmd)) {

		unsigned int scan_period;
@@ -1870,8 +1927,10 @@ static unsigned int labpc_eeprom_read(struct comedi_device *dev, 
				      unsigned int address)

{

	unsigned int value;

	const int read_instruction = 0x3;	/*  bits to tell eeprom to expect a read */

	const int write_length = 8;	/*  8 bit write lengths to eeprom */

	/*  bits to tell eeprom to expect a read */

	const int read_instruction = 0x3;

	/*  8 bit write lengths to eeprom */

	const int write_length = 8;



	/*  enable read/write to eeprom */

	devpriv->command5_bits &= ~EEPROM_EN_BIT;