Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e3d4859e authored by Vivek Aknurwar's avatar Vivek Aknurwar Committed by Gerrit - the friendly Code Review server
Browse files

dt-bindings: clock: add bindings for kona video cc driver 



Added dt-bindings and mm/mx info for kona.

Change-Id: I598aef9b3082d29f15e02e0157e5cc2facbd1eb5
Signed-off-by: default avatarVivek Aknurwar <viveka@codeaurora.org>
parent 87f15eb6

Documentation/devicetree/bindings/clock/qcom,videocc.txt

+21 −1
Original line number Diff line number Diff line
@@ -2,11 +2,18 @@ Qualcomm Video Clock & Reset Controller Binding 
-----------------------------------------------



Required properties :

- compatible : shall contain "qcom,sdm845-videocc"

- compatible : shall contain "qcom,sdm845-videocc" or "qcom,kona-videocc"

- reg : shall contain base register location and length

- clock-names : Shall contain "cfg_ahb_clk"

- clocks : phandle + clock reference to the GCC AHB clock.



- #clock-cells : from common clock binding, shall contain 1.

- #power-domain-cells : from generic power domain binding, shall contain 1.



Required properties (kona only):

- vdd_mm-supply : phandle of the voltage regulator supplying the logic rail

- vdd_mx-supply : phandle of the voltage regulator supplying the memory rail



Optional properties :

- #reset-cells : from common reset binding, shall contain 1.
@@ -17,3 +24,16 @@ Example: 
		#clock-cells = <1>;

		#power-domain-cells = <1>;

		};



Example with vdd mm/mx supply:

	clock_videocc: qcom,videocc@abf0000 {

		compatible = "qcom,videocc-kona";

		reg = <0xabf0000 0x10000>;

		reg-names = "cc_base";

		vdd_mm-supply = <&pm8150a_s5_level>;

		vdd_mx-supply = <&pm8150a_s5_level>;

		clock-names = "cfg_ahb_clk";

		clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

include/dt-bindings/clock/qcom,videocc-kona.h

+15 −11
Original line number Diff line number Diff line
@@ -6,17 +6,21 @@ 


#define VIDEO_CC_AHB_CLK					0

#define VIDEO_CC_AHB_CLK_SRC					1

#define VIDEO_CC_MVS0_CLK					2

#define VIDEO_CC_MVS0_CLK_SRC					3

#define VIDEO_CC_MVS0C_CLK					4

#define VIDEO_CC_MVS1_CLK					5

#define VIDEO_CC_MVS1_CLK_SRC					6

#define VIDEO_CC_MVS1_DIV2_CLK					7

#define VIDEO_CC_MVS1C_CLK					8

#define VIDEO_CC_XO_CLK						9

#define VIDEO_CC_XO_CLK_SRC					10

#define VIDEO_PLL0						11

#define VIDEO_PLL1						12

#define VIDEO_CC_DEBUG_CLK					2

#define VIDEO_CC_MVS0_CLK					3

#define VIDEO_CC_MVS0_CLK_SRC					4

#define VIDEO_CC_MVS0C_CLK					5

#define VIDEO_CC_MVS1_CLK					6

#define VIDEO_CC_MVS1_CLK_SRC					7

#define VIDEO_CC_MVS1_DIV2_CLK					8

#define VIDEO_CC_MVS1C_CLK					9

#define VIDEO_CC_PLL_TEST_CLK					10

#define VIDEO_CC_SLEEP_CLK					11

#define VIDEO_CC_SLEEP_CLK_SRC					12

#define VIDEO_CC_XO_CLK						13

#define VIDEO_CC_XO_CLK_SRC					14

#define VIDEO_PLL0						15

#define VIDEO_PLL1						16



#define MVS0_GDSC						0

#define MVS0C_GDSC						1