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Commit e3cf542a authored by Sunil Paidimarri's avatar Sunil Paidimarri Committed by Suraj Jaiswal
Browse files

data-kernel: EMAC: Enable PPS-LPASS connectivity



Add new flag to the enable PPS-LPASS connectivity
initialziation. Fix the ptp clock frequency
initiazation too the.

Change-Id: I8296306e9223a846a7c57d94231d05488121bcf4
CRs-Fixed: 2374673
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent bd481c87
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+4 −4
Original line number Diff line number Diff line
@@ -5281,10 +5281,10 @@ int ETH_PPSOUT_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data_struct
	int interval, width;
	int interval_ns; /*interval in nano seconds*/

	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1 &&
	if (pdata->res_data->pps_lpass_conn_en &&
		eth_pps_cfg->ptpclk_freq <= 0) {
		/* Set PTP clock to default 250 */
		eth_pps_cfg->ptpclk_freq = DWC_ETH_QOS_DEFAULT_PTP_CLOCK;
		eth_pps_cfg->ptpclk_freq = DWC_ETH_QOS_DEFAULT_LPASS_CLOCK;
	}

	if ((eth_pps_cfg->ppsout_ch < 0) ||
@@ -5323,7 +5323,7 @@ int ETH_PPSOUT_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data_struct

	EMACDBG("PPS: PPSOut_Config: interval=%d, width=%d\n", interval, width);

	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1) {
	if (pdata->res_data->pps_lpass_conn_en) {
		//calculate interval & width
		interval_ns = (1000000000/eth_pps_cfg->ppsout_freq) ;
		interval = ((interval_ns)/4) - 1;
@@ -5333,7 +5333,7 @@ int ETH_PPSOUT_Config(struct DWC_ETH_QOS_prv_data *pdata, struct ifr_data_struct

	switch (eth_pps_cfg->ppsout_ch) {
	case DWC_ETH_QOS_PPS_CH_0:
		if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1) {
		if (pdata->res_data->pps_lpass_conn_en) {
			if (eth_pps_cfg->ppsout_start == DWC_ETH_QOS_PPS_START) {
				MAC_PPSC_PPSEN0_UDFWR(0x1);
				MAC_PPS_INTVAL_PPSINT0_UDFWR(DWC_ETH_QOS_PPS_CH_0, interval);
+5 −0
Original line number Diff line number Diff line
@@ -529,6 +529,7 @@ static void DWC_ETH_QOS_configure_gpio_pins(struct platform_device *pdev)
		dwc_eth_qos_res_data.pinctrl = pinctrl;

		if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_2_0 ||
			dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2 ||
			dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_3_1) {
			/* PPS0 pin */
			emac_pps_0 = pinctrl_lookup_state(pinctrl, EMAC_PIN_PPS0);
@@ -847,6 +848,10 @@ static int DWC_ETH_QOS_get_dts_config(struct platform_device *pdev)
	}
	EMACDBG(": emac_core_version = %d\n", dwc_eth_qos_res_data.emac_hw_version_type);

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_3_1 ||
		dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)
		dwc_eth_qos_res_data.pps_lpass_conn_en = true;

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_3_1) {

		resource = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
+3 −3
Original line number Diff line number Diff line
@@ -315,10 +315,10 @@ int DWC_ETH_QOS_ptp_init(struct DWC_ETH_QOS_prv_data *pdata)
	}

#ifdef CONFIG_PPS_OUTPUT
	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1) {
		/*Configuaring PPS0 PPS output frequency to defualt 19.2 Mhz*/
	if (pdata->res_data->pps_lpass_conn_en) {
		/*Configuring PPS0 PPS output frequency to defualt 19.2 Mhz*/
		eth_pps_cfg.ppsout_ch = 0;
		eth_pps_cfg.ptpclk_freq = DWC_ETH_QOS_DEFAULT_PTP_CLOCK;
		eth_pps_cfg.ptpclk_freq = DWC_ETH_QOS_DEFAULT_LPASS_CLOCK;
		eth_pps_cfg.ppsout_freq = 19200000;
		eth_pps_cfg.ppsout_start = 1;
		req.ptr = (void*)&eth_pps_cfg;
+2 −0
Original line number Diff line number Diff line
@@ -428,6 +428,7 @@ extern void *ipc_emac_log_ctxt;
#define DWC_ETH_QOS_SYSTIMEPERIOD	4 /* System time period is 4ns */

#define DWC_ETH_QOS_DEFAULT_PTP_CLOCK 50000000
#define DWC_ETH_QOS_DEFAULT_LPASS_CLOCK 250000000

#define DWC_ETH_QOS_TX_QUEUE_CNT (pdata->tx_queue_cnt)
#define DWC_ETH_QOS_RX_QUEUE_CNT (pdata->rx_queue_cnt)
@@ -1581,6 +1582,7 @@ struct DWC_ETH_QOS_res_data {
	struct clk *ptp_clk;
	unsigned int emac_hw_version_type;
	bool early_eth_en;
	bool pps_lpass_conn_en;
};

struct DWC_ETH_QOS_prv_ipa_data {