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Commit e3c02009 authored by Jingoo Han's avatar Jingoo Han Committed by Florian Tobias Schandinat
Browse files

video: exynos_dp: add bit-masking for LINK_TRAINING_CTL register 



This patch adds bit-masking for LINK_TRAINING_CTL register, when
pre-emphasis level is set. The bit 3 and bit 2 of LINK_TRAINING_CTL
register are used for pre-emphasis level setting, so other bits
should be masked.

Signed-off-by: default avatarJingoo Han <jg1.han@samsung.com>
Signed-off-by: default avatarFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>
parent 42affc2d

drivers/video/exynos/exynos_dp_reg.c

+12 −4
Original line number Diff line number Diff line
@@ -895,7 +895,9 @@ void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level) 
{

	u32 reg;



	reg = level << PRE_EMPHASIS_SET_SHIFT;

	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);

	reg &= ~PRE_EMPHASIS_SET_MASK;

	reg |= level << PRE_EMPHASIS_SET_SHIFT;

	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);

}
@@ -903,7 +905,9 @@ void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level) 
{

	u32 reg;



	reg = level << PRE_EMPHASIS_SET_SHIFT;

	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);

	reg &= ~PRE_EMPHASIS_SET_MASK;

	reg |= level << PRE_EMPHASIS_SET_SHIFT;

	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);

}
@@ -911,7 +915,9 @@ void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level) 
{

	u32 reg;



	reg = level << PRE_EMPHASIS_SET_SHIFT;

	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);

	reg &= ~PRE_EMPHASIS_SET_MASK;

	reg |= level << PRE_EMPHASIS_SET_SHIFT;

	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);

}
@@ -919,7 +925,9 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level) 
{

	u32 reg;



	reg = level << PRE_EMPHASIS_SET_SHIFT;

	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);

	reg &= ~PRE_EMPHASIS_SET_MASK;

	reg |= level << PRE_EMPHASIS_SET_SHIFT;

	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);

}

drivers/video/exynos/exynos_dp_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -285,6 +285,7 @@ 
#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)



/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */

#define PRE_EMPHASIS_SET_MASK			(0x3 << 3)

#define PRE_EMPHASIS_SET_SHIFT			(3)



/* EXYNOS_DP_DEBUG_CTL */