Loading drivers/dma/dw/Kconfig +2 −9 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ config DW_DMAC_CORE config DW_DMAC tristate "Synopsys DesignWare AHB DMA platform driver" select DW_DMAC_CORE select DW_DMAC_BIG_ENDIAN_IO if AVR32 default y if CPU_AT32AP7000 help Support the Synopsys DesignWare AHB DMA controller. This Loading @@ -25,12 +26,4 @@ config DW_DMAC_PCI Intel Medfield has integrated this GPDMA controller. config DW_DMAC_BIG_ENDIAN_IO bool "Use big endian I/O register access" default y if AVR32 depends on DW_DMAC_CORE help Say yes here to use big endian I/O access when reading and writing to the DMA controller registers. This is needed on some platforms, like the Atmel AVR32 architecture. If unsure, use the default setting. bool drivers/dma/dw/regs.h +6 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,12 @@ struct dw_dma_regs { u32 DW_PARAMS; }; /* * Big endian I/O access when reading and writing to the DMA controller * registers. This is needed on some platforms, like the Atmel AVR32 * architecture. */ #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO #define dma_readl_native ioread32be #define dma_writel_native iowrite32be Loading Loading
drivers/dma/dw/Kconfig +2 −9 Original line number Diff line number Diff line Loading @@ -10,6 +10,7 @@ config DW_DMAC_CORE config DW_DMAC tristate "Synopsys DesignWare AHB DMA platform driver" select DW_DMAC_CORE select DW_DMAC_BIG_ENDIAN_IO if AVR32 default y if CPU_AT32AP7000 help Support the Synopsys DesignWare AHB DMA controller. This Loading @@ -25,12 +26,4 @@ config DW_DMAC_PCI Intel Medfield has integrated this GPDMA controller. config DW_DMAC_BIG_ENDIAN_IO bool "Use big endian I/O register access" default y if AVR32 depends on DW_DMAC_CORE help Say yes here to use big endian I/O access when reading and writing to the DMA controller registers. This is needed on some platforms, like the Atmel AVR32 architecture. If unsure, use the default setting. bool
drivers/dma/dw/regs.h +6 −0 Original line number Diff line number Diff line Loading @@ -101,6 +101,12 @@ struct dw_dma_regs { u32 DW_PARAMS; }; /* * Big endian I/O access when reading and writing to the DMA controller * registers. This is needed on some platforms, like the Atmel AVR32 * architecture. */ #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO #define dma_readl_native ioread32be #define dma_writel_native iowrite32be Loading
Vinod Koul <vinod.koul@intel.com>Vinod Koul <vinod.koul@intel.com>