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Commit e351cc94 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add and expose true inline rot prefill parameters"

parents ac886c6d 531569ea

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+9 −0
Original line number Diff line number Diff line
@@ -1137,6 +1137,12 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
			sde_cfg->true_inline_dwnscale_nrt;

		sblk->in_rot_maxheight =

			MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT;

		sblk->in_rot_prefill_fudge_lines =

			sde_cfg->true_inline_prefill_fudge_lines;

		sblk->in_rot_prefill_lines_nv12 =

			sde_cfg->true_inline_prefill_lines_nv12;

		sblk->in_rot_prefill_lines =

			sde_cfg->true_inline_prefill_lines;

	}



	if (sde_cfg->sc_cfg.has_sys_cache) {
@@ -3807,6 +3813,9 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DEFAULT;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

		sde_cfg->uidle_cfg.uidle_rev = SDE_UIDLE_VERSION_1_0_0;

	} else {

		SDE_ERROR("unsupported chipset id:%X\n", hw_rev);

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+12 −0
Original line number Diff line number Diff line
@@ -591,6 +591,9 @@ struct sde_qos_lut_tbl { 
 * @in_rot_maxdwnscale_rt: max downscale ratio for inline rotation rt clients

 * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients

 * @in_rot_maxheight: max pre rotated height for inline rotation

 * @in_rot_prefill_fudge_lines: prefill fudge lines for inline rotation

 * @in_rot_prefill_lines_mv12: prefill lines for nv12 format inline rotation

 * @in_rot_prefill_lines: prefill lines for inline rotation

 * @llcc_scid: scid for the system cache

 * @llcc_slice size: slice size of the system cache

 */
@@ -625,6 +628,9 @@ struct sde_sspp_sub_blks { 
	u32 in_rot_maxdwnscale_rt;

	u32 in_rot_maxdwnscale_nrt;

	u32 in_rot_maxheight;

	u32 in_rot_prefill_fudge_lines;

	u32 in_rot_prefill_lines_nv12;

	u32 in_rot_prefill_lines;

	int llcc_scid;

	size_t llcc_slice_size;

};
@@ -1155,6 +1161,9 @@ struct sde_perf_cfg { 
 * @true_inline_rot_rev	inline rotator feature revision

 * @true_inline_dwnscale_rt    true inline rotator downscale ratio for rt

 * @true_inline_dwnscale_nrt    true inline rotator downscale ratio for nrt

 * @true_inline_prefill_fudge_lines    true inline rotator prefill fudge lines

 * @true_inline_prefill_lines_nv12    true inline prefill lines for nv12 format

 * @true_inline_prefill_lines    true inline prefill lines

 * @macrotile_mode     UBWC parameter for macro tile channel distribution

 * @pipe_order_type    indicate if it is required to specify pipe order

 * @delay_prg_fetch_start indicates if throttling the fetch start is required
@@ -1208,6 +1217,9 @@ struct sde_mdss_cfg { 
	u32 true_inline_rot_rev;

	u32 true_inline_dwnscale_rt;

	u32 true_inline_dwnscale_nrt;

	u32 true_inline_prefill_fudge_lines;

	u32 true_inline_prefill_lines_nv12;

	u32 true_inline_prefill_lines;

	u32 macrotile_mode;

	u32 pipe_order_type;

	bool delay_prg_fetch_start;

drivers/gpu/drm/msm/sde/sde_plane.c

+6 −0
Original line number Diff line number Diff line
@@ -3532,6 +3532,12 @@ static void _sde_plane_install_properties(struct drm_plane *plane, 
			psde->pipe_sblk->in_rot_maxdwnscale_nrt);

		sde_kms_info_add_keyint(info, "true_inline_max_height",

			psde->pipe_sblk->in_rot_maxheight);

		sde_kms_info_add_keyint(info, "true_inline_prefill_fudge_lines",

			psde->pipe_sblk->in_rot_prefill_fudge_lines);

		sde_kms_info_add_keyint(info, "true_inline_prefill_lines_nv12",

			psde->pipe_sblk->in_rot_prefill_lines_nv12);

		sde_kms_info_add_keyint(info, "true_inline_prefill_lines",

			psde->pipe_sblk->in_rot_prefill_lines);



		inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;