Merge "iommu: Add msm_iommu_ops for qcom specific IOMMU ops" (e33b179d) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/iommu/arm-smmu.c

+0 −61

Original line number	Diff line number	Diff line
		@@ -3931,65 +3931,6 @@ static void arm_smmu_trigger_fault(struct iommu_domain *domain,
		arm_smmu_power_off(smmu->pwr);
		}

		static unsigned long arm_smmu_reg_read(struct iommu_domain *domain,
		unsigned long offset)
		{
		struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
		struct arm_smmu_device *smmu;
		struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
		void __iomem *cb_base;
		unsigned long val;

		if (offset >= SZ_4K) {
		pr_err("Invalid offset: 0x%lx\n", offset);
		return 0;
		}

		smmu = smmu_domain->smmu;
		if (!smmu) {
		WARN(1, "Can't read registers of a detached domain\n");
		val = 0;
		return val;
		}

		if (arm_smmu_power_on(smmu->pwr))
		return 0;

		cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
		val = readl_relaxed(cb_base + offset);

		arm_smmu_power_off(smmu->pwr);
		return val;
		}

		static void arm_smmu_reg_write(struct iommu_domain *domain,
		unsigned long offset, unsigned long val)
		{
		struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
		struct arm_smmu_device *smmu;
		struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
		void __iomem *cb_base;

		if (offset >= SZ_4K) {
		pr_err("Invalid offset: 0x%lx\n", offset);
		return;
		}

		smmu = smmu_domain->smmu;
		if (!smmu) {
		WARN(1, "Can't read registers of a detached domain\n");
		return;
		}

		if (arm_smmu_power_on(smmu->pwr))
		return;

		cb_base = ARM_SMMU_CB(smmu, cfg->cbndx);
		writel_relaxed(val, cb_base + offset);

		arm_smmu_power_off(smmu->pwr);
		}

		static void arm_smmu_tlbi_domain(struct iommu_domain *domain)
		{
		arm_smmu_tlb_inv_context_s1(to_smmu_domain(domain));
		@@ -4030,8 +3971,6 @@ static struct iommu_ops arm_smmu_ops = {
		.put_resv_regions = arm_smmu_put_resv_regions,
		.pgsize_bitmap = -1UL, /* Restricted during device attach */
		.trigger_fault = arm_smmu_trigger_fault,
		.reg_read = arm_smmu_reg_read,
		.reg_write = arm_smmu_reg_write,
		.tlbi_domain = arm_smmu_tlbi_domain,
		.enable_config_clocks = arm_smmu_enable_config_clocks,
		.disable_config_clocks = arm_smmu_disable_config_clocks,

drivers/iommu/iommu.c

+0 −25

Original line number	Diff line number	Diff line
		@@ -1931,31 +1931,6 @@ void iommu_trigger_fault(struct iommu_domain *domain, unsigned long flags)
		domain->ops->trigger_fault(domain, flags);
		}

		/**
		* iommu_reg_read() - read an IOMMU register
		*
		* Reads the IOMMU register at the given offset.
		*/
		unsigned long iommu_reg_read(struct iommu_domain *domain, unsigned long offset)
		{
		if (domain->ops->reg_read)
		return domain->ops->reg_read(domain, offset);
		return 0;
		}

		/**
		* iommu_reg_write() - write an IOMMU register
		*
		* Writes the given value to the IOMMU register at the given offset.
		*/
		void iommu_reg_write(struct iommu_domain *domain, unsigned long offset,
		unsigned long val)
		{
		if (domain->ops->reg_write)
		domain->ops->reg_write(domain, offset, val);
		}


		struct iommu_resv_region *iommu_alloc_resv_region(phys_addr_t start,
		size_t length, int prot,
		enum iommu_resv_type type)

include/linux/iommu.h

+30 −6

Original line number	Diff line number	Diff line
		@@ -99,6 +99,8 @@ struct iommu_pgtbl_info {
		#define IOMMU_DOMAIN_DMA (__IOMMU_DOMAIN_PAGING \| \
		__IOMMU_DOMAIN_DMA_API)

		#define to_msm_iommu_ops(_iommu_ops) \
		container_of(_iommu_ops, struct msm_iommu_ops, iommu_ops)

		#define IOMMU_DOMAIN_NAME_LEN 32
		struct iommu_domain {
		@@ -233,8 +235,6 @@ extern struct dentry *iommu_debugfs_top;
		* @of_xlate: add OF master IDs to iommu grouping
		* @pgsize_bitmap: bitmap of all possible supported page sizes
		* @trigger_fault: trigger a fault on the device attached to an iommu domain
		* @reg_read: read an IOMMU register
		* @reg_write: write an IOMMU register
		* @tlbi_domain: Invalidate all TLBs covering an iommu domain
		* @enable_config_clocks: Enable all config clocks for this domain's IOMMU
		* @disable_config_clocks: Disable all config clocks for this domain's IOMMU
		@@ -285,10 +285,6 @@ struct iommu_ops {
		/* Get the number of windows per domain */
		u32 (domain_get_windows)(struct iommu_domain domain);
		void (trigger_fault)(struct iommu_domain domain, unsigned long flags);
		unsigned long (reg_read)(struct iommu_domain domain,
		unsigned long offset);
		void (reg_write)(struct iommu_domain domain, unsigned long val,
		unsigned long offset);
		void (tlbi_domain)(struct iommu_domain domain);
		int (enable_config_clocks)(struct iommu_domain domain);
		void (disable_config_clocks)(struct iommu_domain domain);
		@@ -302,6 +298,34 @@ struct iommu_ops {
		unsigned long pgsize_bitmap;
		};

		/**
		* struct msm_iommu_ops - standard iommu ops, as well as additional MSM
		* specific iommu ops
		* @map_sg: map a scatter-gather list of physically contiguous memory chunks
		* to an iommu domain
		* @iova_to_phys_hard: translate iova to physical address using IOMMU hardware
		* @is_iova_coherent: checks coherency of the given iova
		* @trigger_fault: trigger a fault on the device attached to an iommu domain
		* @tlbi_domain: Invalidate all TLBs covering an iommu domain
		* @enable_config_clocks: Enable all config clocks for this domain's IOMMU
		* @disable_config_clocks: Disable all config clocks for this domain's IOMMU
		* @iova_to_pte: translate iova to Page Table Entry (PTE).
		* @iommu_ops: the standard iommu ops
		*/
		struct msm_iommu_ops {
		size_t (map_sg)(struct iommu_domain domain, unsigned long iova,
		struct scatterlist *sg, unsigned int nents, int prot);
		phys_addr_t (iova_to_phys_hard)(struct iommu_domain domain,
		dma_addr_t iova);
		bool (is_iova_coherent)(struct iommu_domain domain, dma_addr_t iova);
		void (trigger_fault)(struct iommu_domain domain, unsigned long flags);
		void (tlbi_domain)(struct iommu_domain domain);
		int (enable_config_clocks)(struct iommu_domain domain);
		void (disable_config_clocks)(struct iommu_domain domain);
		uint64_t (iova_to_pte)(struct iommu_domain domain, dma_addr_t iova);
		struct iommu_ops iommu_ops;
		};

		/**
		* struct iommu_device - IOMMU core representation of one IOMMU hardware
		* instance