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Commit e2a4f0d2 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru Committed by Nirmal Abraham
Browse files

msm: mdss: add support for DSI 12nm PHY in DSI driver 



Add support for DSI 12nm PHY programming in the DSI driver as per
the recommended DSI PHY programming sequence.

Change-Id: Ic2c6eed0147903970da85781818d8ccd94c40021
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent edde3db9

drivers/video/fbdev/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ mdss-dsi-objs += mdss_dsi_panel.o 
mdss-dsi-objs += msm_mdss_io_8974.o

mdss-dsi-objs += mdss_dsi_phy.o

mdss-dsi-objs += mdss_dsi_phy_v3.o

mdss-dsi-objs += mdss_dsi_phy_12nm.o

mdss-dsi-objs += mdss_dsi_clk.o

obj-$(CONFIG_FB_MSM_MDSS) += mdss-dsi.o

obj-$(CONFIG_FB_MSM_MDSS) += mdss_panel.o

drivers/video/fbdev/msm/mdss_dsi.c

+9 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */



#include <linux/module.h>

#include <linux/interrupt.h>
@@ -4394,11 +4394,11 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, 
	if (!data) {

		pr_err("%s:%d, Unable to read Phy Strength ctrl settings\n",

			__func__, __LINE__);

		return -EINVAL;

	}

	} else {

		pinfo->mipi.dsi_phy_db.strength_len = len;

		for (i = 0; i < len; i++)

			pinfo->mipi.dsi_phy_db.strength[i] = data[i];

	}



	pinfo->mipi.dsi_phy_db.reg_ldo_mode = of_property_read_bool(

		ctrl_pdev->dev.of_node, "qcom,regulator-ldo-mode");
@@ -4429,11 +4429,11 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev, 
	if (!data) {

		pr_err("%s:%d, Unable to read Phy lane configure settings\n",

			__func__, __LINE__);

		return -EINVAL;

	}

	} else {

		pinfo->mipi.dsi_phy_db.lanecfg_len = len;

		for (i = 0; i < len; i++)

			pinfo->mipi.dsi_phy_db.lanecfg[i] = data[i];

	}



	ctrl_pdata->timing_db_mode = of_property_read_bool(

		ctrl_pdev->dev.of_node, "qcom,timing-db-mode");

drivers/video/fbdev/msm/mdss_dsi.h

+2 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */



#ifndef MDSS_DSI_H

#define MDSS_DSI_H
@@ -350,6 +350,7 @@ struct dsi_panel_timing { 
	struct mdss_panel_timing timing;

	uint32_t phy_timing[12];

	uint32_t phy_timing_8996[40];

	uint32_t phy_timing_12nm[8];

	/* DSI_CLKOUT_TIMING_CTRL */

	char t_clk_post;

	char t_clk_pre;

drivers/video/fbdev/msm/mdss_dsi_host.c

+29 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2012-2018, 2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2012-2018, 2020-2021, The Linux Foundation. All rights reserved. */



#include <linux/module.h>

#include <linux/interrupt.h>
@@ -296,6 +296,30 @@ void mdss_dsi_read_phy_revision(struct mdss_dsi_ctrl_pdata *ctrl) 
		return;



	reg_val = MIPI_INP(ctrl->phy_io.base);

	if (!reg_val) {

		/*

		 * DSI_0_PHY_DSIPHY_REVISION_ID3 for phy 1.0

		 * reset value = 0x10

		 * 7:4 Major

		 * 3:0 Minor

		 */

		reg_val = MIPI_INP(ctrl->phy_io.base + 0x20c);

		reg_val = reg_val >> 4;

		if (!reg_val) {

			/*

			 * DSI_0_PHY_DSIPHY_REVISION_ID3 for 12nm PHY

			 * reset value = 0x20

			 * 7:4 Major

			 * 3:0 Minor

			 */

			reg_val = MIPI_INP(ctrl->phy_io.base + 0x3dc);

			reg_val = reg_val >> 4;

			if (reg_val == 0x2) {

				ctrl->shared_data->phy_rev = DSI_PHY_REV_12NM;

				return;

			}

		}

	}



	if (reg_val == DSI_PHY_REV_30)

		ctrl->shared_data->phy_rev = DSI_PHY_REV_30;
@@ -418,6 +442,9 @@ void mdss_dsi_host_init(struct mdss_panel_data *pdata) 


	mdss_dsi_config_data_lane_swap(ctrl_pdata);



	if (ctrl_pdata->shared_data->phy_rev == DSI_PHY_REV_12NM)

		goto next;



	/* clock out ctrl */

	data = pinfo->t_clk_post & 0x3f;	/* 6 bits */

	data <<= 8;
@@ -425,6 +452,7 @@ void mdss_dsi_host_init(struct mdss_panel_data *pdata) 
	/* DSI_CLKOUT_TIMING_CTRL */

	MIPI_OUTP((ctrl_pdata->ctrl_base) + 0xc4, data);



next:

	data = 0;

	if (pinfo->rx_eot_ignore)

		data |= BIT(4);

drivers/video/fbdev/msm/mdss_dsi_panel.c

+16 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */



#include <linux/module.h>

#include <linux/interrupt.h>
@@ -2504,6 +2504,9 @@ int mdss_dsi_panel_timing_switch(struct mdss_dsi_ctrl_pdata *ctrl, 
	for (i = 0; i < ARRAY_SIZE(pt->phy_timing_8996); i++)

		pinfo->mipi.dsi_phy_db.timing_8996[i] = pt->phy_timing_8996[i];



	for (i = 0; i < ARRAY_SIZE(pt->phy_timing_12nm); i++)

		pinfo->mipi.dsi_phy_db.timing_12nm[i] = pt->phy_timing_12nm[i];



	ctrl->on_cmds = pt->on_cmds;

	ctrl->post_panel_on_cmds = pt->post_panel_on_cmds;
@@ -2617,6 +2620,18 @@ static int mdss_dsi_panel_timing_from_dt(struct device_node *np, 
			pt->phy_timing_8996[i] = data[i];

		phy_timings_present = true;

	}



	data = of_get_property(np,

		"qcom,mdss-dsi-panel-timings-phy-12nm", &len);

	if ((!data) || (len != 8)) {

		pr_debug("%s:%d,Unable to read 12nm Phy lane timing settings\n",

		       __func__, __LINE__);

	} else {

		for (i = 0; i < len; i++)

			pt->phy_timing_12nm[i] = data[i];

		phy_timings_present = true;

	}



	if (!phy_timings_present) {

		pr_err("%s: phy timing settings not present\n", __func__);

		return -EINVAL;