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Commit e187837b authored by Barry Song's avatar Barry Song Committed by Mike Frysinger
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Blackfin: MPU: support XIP in async flash memory 



The NOMPU code already supported executing in the async banks, so this
brings the MPU code in line.

Signed-off-by: default avatarBarry Song <barry.song@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent d45e8db1

arch/blackfin/kernel/cplb-mpu/cplbmgr.c

+9 −4
Original line number Diff line number Diff line
@@ -113,11 +113,11 @@ static noinline int dcplb_miss(unsigned int cpu) 
		addr = L2_START;

		d_data = L2_DMEMORY;

	} else if (addr >= physical_mem_end) {

		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE

		    && (status & FAULT_USERSUPV)) {

			addr &= ~0x3fffff;

		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {

			addr &= ~(4 * 1024 * 1024 - 1);

			d_data &= ~PAGE_SIZE_4KB;

			d_data |= PAGE_SIZE_4MB;

			d_data |= CPLB_USER_RD | CPLB_USER_WR;

		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH

		    && (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {

			addr &= ~(1 * 1024 * 1024 - 1);
@@ -203,7 +203,12 @@ static noinline int icplb_miss(unsigned int cpu) 
		addr = L2_START;

		i_data = L2_IMEMORY;

	} else if (addr >= physical_mem_end) {

		if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH

		if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {

			addr &= ~(4 * 1024 * 1024 - 1);

			i_data &= ~PAGE_SIZE_4KB;

			i_data |= PAGE_SIZE_4MB;

			i_data |= CPLB_USER_RD;

		} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH

		    && (status & FAULT_USERSUPV)) {

			addr &= ~(1 * 1024 * 1024 - 1);

			i_data &= ~PAGE_SIZE_4KB;