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Commit e16fd002 authored by Grzegorz Andrejczuk's avatar Grzegorz Andrejczuk Committed by Thomas Gleixner
Browse files

x86/cpufeature: Enable RING3MWAIT for Knights Landing 



Enable ring 3 MONITOR/MWAIT for Intel Xeon Phi x200 codenamed Knights
Landing.

Presence of this feature cannot be detected automatically (by reading any
other MSR) therefore it is required to explicitly check for the family and
model of the CPU before attempting to enable it.

Signed-off-by: default avatarGrzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: Piotr.Luc@intel.com
Cc: dave.hansen@linux.intel.com
Link: http://lkml.kernel.org/r/1484918557-15481-5-git-send-email-grzegorz.andrejczuk@intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 1d12d0ef

Documentation/admin-guide/kernel-parameters.txt

+4 −0
Original line number Diff line number Diff line
@@ -3563,6 +3563,10 @@ 
	rhash_entries=	[KNL,NET]

			Set number of hash buckets for route cache



	ring3mwait=disable

			[KNL] Disable ring 3 MONITOR/MWAIT feature on supported

			CPUs.



	ro		[KNL] Mount root device read-only on boot



	rodata=		[KNL]

arch/x86/kernel/cpu/intel.c

+37 −0
Original line number Diff line number Diff line
@@ -15,6 +15,8 @@ 
#include <asm/cpu.h>

#include <asm/intel-family.h>

#include <asm/microcode_intel.h>

#include <asm/hwcap2.h>

#include <asm/elf.h>



#ifdef CONFIG_X86_64

#include <linux/topology.h>
@@ -62,6 +64,39 @@ void check_mpx_erratum(struct cpuinfo_x86 *c) 
	}

}



static bool ring3mwait_disabled __read_mostly;



static int __init ring3mwait_disable(char *__unused)

{

	ring3mwait_disabled = true;

	return 0;

}

__setup("ring3mwait=disable", ring3mwait_disable);



static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)

{

	/*

	 * Ring 3 MONITOR/MWAIT feature cannot be detected without

	 * cpu model and family comparison.

	 */

	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)

		return;



	if (ring3mwait_disabled) {

		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,

			      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);

		return;

	}



	msr_set_bit(MSR_MISC_FEATURE_ENABLES,

		    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);



	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);



	if (c == &boot_cpu_data)

		ELF_HWCAP2 |= HWCAP2_RING3MWAIT;

}



static void early_init_intel(struct cpuinfo_x86 *c)

{

	u64 misc_enable;
@@ -560,6 +595,8 @@ static void init_intel(struct cpuinfo_x86 *c) 
		detect_vmx_virtcap(c);



	init_intel_energy_perf(c);



	probe_xeon_phi_r3mwait(c);

}



#ifdef CONFIG_X86_32