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Commit e102da49 authored by Xingyu Chen's avatar Xingyu Chen Committed by Kevin Hilman
Browse files

ARM64: dts: meson: drop "sana" clock from SAR ADC 



The SAR ADC modules doesn't require The "sana" clock.

Acked-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Singed-off-by: default avatarXingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
Signed-off-by: default avatarKevin Hilman <khilman@baylibre.com>
parent fc19afa1

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

+1 −2
Original line number Diff line number Diff line
@@ -740,10 +740,9 @@ 
	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";

	clocks = <&xtal>,

		 <&clkc CLKID_SAR_ADC>,

		 <&clkc CLKID_SANA>,

		 <&clkc CLKID_SAR_ADC_CLK>,

		 <&clkc CLKID_SAR_ADC_SEL>;

	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";

	clock-names = "clkin", "core", "adc_clk", "adc_sel";

};



&sd_emmc_a {

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

+1 −2
Original line number Diff line number Diff line
@@ -690,10 +690,9 @@ 
	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";

	clocks = <&xtal>,

		 <&clkc CLKID_SAR_ADC>,

		 <&clkc CLKID_SANA>,

		 <&clkc CLKID_SAR_ADC_CLK>,

		 <&clkc CLKID_SAR_ADC_SEL>;

	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";

	clock-names = "clkin", "core", "adc_clk", "adc_sel";

};



&sd_emmc_a {