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Commit e0fc736e authored by Taniya's avatar Taniya
Browse files

ARM: dts: msm: Add Video efuse region in QFPROM for LITO 

Add the video efuse and also update the videocc node with the nvmem phandle
to read the efuse.

Change-Id: If747ca171ee7da8ae5da7d9ee5c577eb89a2ea70
parent 4d449f4a

bindings/clock/qcom,videocc.txt

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,8 @@ Required properties (kona only): 


Optional properties :

- #reset-cells : from common reset binding, shall contain 1.

- nvmem-cells: list of phandle to the nvmem data cells.

- nvmem-cell-names: names for the each nvmem-cells specified.



Example:

	videocc: clock-controller@ab00000 {

qcom/lito.dtsi

+11 −6
Original line number Diff line number Diff line
@@ -1869,12 +1869,13 @@ 


	videocc: qcom,videocc@ab00000 {

		compatible = "qcom,lito-videocc", "syscon";

		reg = <0x0ab00000 0x10000>,

			<0x786008 0x4>;

		reg-names = "cc_base", "efuse";

		reg = <0x0ab00000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_VIDEO_AHB_CLK>;

		nvmem-cells = <&iris_efuse>;

		nvmem-cell-names = "iris-bin";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -3572,9 +3573,9 @@ 
		memory-region = <&pil_npu_mem>;

	};



	qfprom: qfprom@0x780000 {

	qfprom: qfprom@780000 {

		compatible = "qcom,qfprom";

		reg = <0x00780000 0x1000>;

		reg = <0x00780000 0x7000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;
@@ -3589,10 +3590,14 @@ 
			bits = <0 1>;

		};



		adsp_variant: adsp_variant@0x780210 {

		adsp_variant: adsp_variant@210 {

			reg = <0x210 0x4>;

			bits = <0x0 0x20>;

		};



		iris_efuse: iris@6008 {

			reg = <0x6008 0x4>;

		};

	};

};