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Commit e0bc14c6 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Add rscc registers to a650 snapshot 



A650 has new rscc registers so dump them in snapshot.
Also, dump them before checking whether gx is on
because rscc registers are in cx.

Change-Id: Iad8063e6bd3a806d3e7cd1d637e451cf6e0d9d55
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 364475ab

drivers/gpu/msm/adreno_a6xx_snapshot.c

+113 −10
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 */



#include <linux/io.h>
@@ -66,6 +66,56 @@ static const unsigned int a6xx_rscc_snapshot_registers[] = { 
	0x2389C, 0x238D7, 0x2393C, 0x2393F, 0x23944, 0x2397F,

};



static const unsigned int a650_rscc_registers[] = {

	0x38000, 0x38034, 0x38036, 0x38036, 0x38040, 0x38042, 0x38080, 0x38084,

	0x38089, 0x3808C, 0x38091, 0x38094, 0x38099, 0x3809C, 0x380A1, 0x380A4,

	0x380A9, 0x380AC, 0x38100, 0x38102, 0x38104, 0x38107, 0x38114, 0x38119,

	0x38124, 0x3812E, 0x38180, 0x38197, 0x38340, 0x38341, 0x38344, 0x38347,

	0x3834C, 0x3834F, 0x38351, 0x38354, 0x38356, 0x38359, 0x3835B, 0x3835E,

	0x38360, 0x38363, 0x38365, 0x38368, 0x3836A, 0x3836D, 0x3836F, 0x38372,

	0x383EC, 0x383EF, 0x383F4, 0x383F7, 0x383F9, 0x383FC, 0x383FE, 0x38401,

	0x38403, 0x38406, 0x38408, 0x3840B, 0x3840D, 0x38410, 0x38412, 0x38415,

	0x38417, 0x3841A, 0x38494, 0x38497, 0x3849C, 0x3849F, 0x384A1, 0x384A4,

	0x384A6, 0x384A9, 0x384AB, 0x384AE, 0x384B0, 0x384B3, 0x384B5, 0x384B8,

	0x384BA, 0x384BD, 0x384BF, 0x384C2, 0x3853C, 0x3853F, 0x38544, 0x38547,

	0x38549, 0x3854C, 0x3854E, 0x38551, 0x38553, 0x38556, 0x38558, 0x3855B,

	0x3855D, 0x38560, 0x38562, 0x38565, 0x38567, 0x3856A, 0x385E4, 0x385E7,

	0x385EC, 0x385EF, 0x385F1, 0x385F4, 0x385F6, 0x385F9, 0x385FB, 0x385FE,

	0x38600, 0x38603, 0x38605, 0x38608, 0x3860A, 0x3860D, 0x3860F, 0x38612,

	0x3868C, 0x3868F, 0x38694, 0x38697, 0x38699, 0x3869C, 0x3869E, 0x386A1,

	0x386A3, 0x386A6, 0x386A8, 0x386AB, 0x386AD, 0x386B0, 0x386B2, 0x386B5,

	0x386B7, 0x386BA, 0x38734, 0x38737, 0x3873C, 0x3873F, 0x38741, 0x38744,

	0x38746, 0x38749, 0x3874B, 0x3874E, 0x38750, 0x38753, 0x38755, 0x38758,

	0x3875A, 0x3875D, 0x3875F, 0x38762, 0x387DC, 0x387DF, 0x387E4, 0x387E7,

	0x387E9, 0x387EC, 0x387EE, 0x387F1, 0x387F3, 0x387F6, 0x387F8, 0x387FB,

	0x387FD, 0x38800, 0x38802, 0x38805, 0x38807, 0x3880A, 0x38884, 0x38887,

	0x3888C, 0x3888F, 0x38891, 0x38894, 0x38896, 0x38899, 0x3889B, 0x3889E,

	0x388A0, 0x388A3, 0x388A5, 0x388A8, 0x388AA, 0x388AD, 0x388AF, 0x388B2,

	0x3892C, 0x3892F, 0x38934, 0x38937, 0x38939, 0x3893C, 0x3893E, 0x38941,

	0x38943, 0x38946, 0x38948, 0x3894B, 0x3894D, 0x38950, 0x38952, 0x38955,

	0x38957, 0x3895A, 0x38B50, 0x38B51, 0x38B53, 0x38B55, 0x38B5A, 0x38B5A,

	0x38B5F, 0x38B5F, 0x38B64, 0x38B64, 0x38B69, 0x38B69, 0x38B6E, 0x38B6E,

	0x38B73, 0x38B73, 0x38BF8, 0x38BF8, 0x38BFD, 0x38BFD, 0x38C02, 0x38C02,

	0x38C07, 0x38C07, 0x38C0C, 0x38C0C, 0x38C11, 0x38C11, 0x38C16, 0x38C16,

	0x38C1B, 0x38C1B, 0x38CA0, 0x38CA0, 0x38CA5, 0x38CA5, 0x38CAA, 0x38CAA,

	0x38CAF, 0x38CAF, 0x38CB4, 0x38CB4, 0x38CB9, 0x38CB9, 0x38CBE, 0x38CBE,

	0x38CC3, 0x38CC3, 0x38D48, 0x38D48, 0x38D4D, 0x38D4D, 0x38D52, 0x38D52,

	0x38D57, 0x38D57, 0x38D5C, 0x38D5C, 0x38D61, 0x38D61, 0x38D66, 0x38D66,

	0x38D6B, 0x38D6B, 0x38DF0, 0x38DF0, 0x38DF5, 0x38DF5, 0x38DFA, 0x38DFA,

	0x38DFF, 0x38DFF, 0x38E04, 0x38E04, 0x38E09, 0x38E09, 0x38E0E, 0x38E0E,

	0x38E13, 0x38E13, 0x38E98, 0x38E98, 0x38E9D, 0x38E9D, 0x38EA2, 0x38EA2,

	0x38EA7, 0x38EA7, 0x38EAC, 0x38EAC, 0x38EB1, 0x38EB1, 0x38EB6, 0x38EB6,

	0x38EBB, 0x38EBB, 0x38F40, 0x38F40, 0x38F45, 0x38F45, 0x38F4A, 0x38F4A,

	0x38F4F, 0x38F4F, 0x38F54, 0x38F54, 0x38F59, 0x38F59, 0x38F5E, 0x38F5E,

	0x38F63, 0x38F63, 0x38FE8, 0x38FE8, 0x38FED, 0x38FED, 0x38FF2, 0x38FF2,

	0x38FF7, 0x38FF7, 0x38FFC, 0x38FFC, 0x39001, 0x39001, 0x39006, 0x39006,

	0x3900B, 0x3900B, 0x39090, 0x39090, 0x39095, 0x39095, 0x3909A, 0x3909A,

	0x3909F, 0x3909F, 0x390A4, 0x390A4, 0x390A9, 0x390A9, 0x390AE, 0x390AE,

	0x390B3, 0x390B3, 0x39138, 0x39138, 0x3913D, 0x3913D, 0x39142, 0x39142,

	0x39147, 0x39147, 0x3914C, 0x3914C, 0x39151, 0x39151, 0x39156, 0x39156,

	0x3915B, 0x3915B,

};



static const struct sel_reg {

	unsigned int host_reg;

	unsigned int cd_reg;
@@ -1489,6 +1539,48 @@ static void _a6xx_do_crashdump(struct kgsl_device *device) 
	crash_dump_valid = true;

}



size_t a6xx_snapshot_rscc_registers(struct kgsl_device *device, u8 *buf,

	size_t remain, void *priv)

{

	struct kgsl_snapshot_regs *header = (struct kgsl_snapshot_regs *)buf;

	struct kgsl_snapshot_registers *regs = priv;

	unsigned int *data = (unsigned int *)(buf + sizeof(*header));

	int count = 0, j, k;

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);



	/* Figure out how many registers we are going to dump */

	for (j = 0; j < regs->count; j++) {

		int start = regs->regs[j * 2];

		int end = regs->regs[j * 2 + 1];



		count += (end - start + 1);

	}



	if (remain < (count * 8) + sizeof(*header)) {

		SNAPSHOT_ERR_NOMEM(device, "RSCC REGISTERS");

		return 0;

	}



	for (j = 0; j < regs->count; j++) {

		unsigned int start = regs->regs[j * 2];

		unsigned int end = regs->regs[j * 2 + 1];



		for (k = start; k <= end; k++) {

			unsigned int val;



			adreno_rscc_regread(adreno_dev,

				k - (adreno_dev->rscc_base >> 2), &val);

			*data++ = k;

			*data++ = val;

		}

	}



	header->count = count;



	/* Return the size of the section */

	return (count * 8) + sizeof(*header);

}



/*

 * a6xx_snapshot() - A6XX GPU snapshot function

 * @adreno_dev: Device being snapshotted
@@ -1517,6 +1609,26 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
	 */

	a6xx_snapshot_debugbus(adreno_dev, snapshot);



	/* RSCC registers are on cx */

	if (adreno_is_a650(adreno_dev)) {

		struct kgsl_snapshot_registers r;



		r.regs = a650_rscc_registers;

		r.count = ARRAY_SIZE(a650_rscc_registers) / 2;



		kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS,

			snapshot, a6xx_snapshot_rscc_registers, &r);

	} else if (adreno_is_a615_family(adreno_dev) ||

			adreno_is_a630(adreno_dev)) {

		adreno_snapshot_registers(device, snapshot,

			a630_rscc_snapshot_registers,

			ARRAY_SIZE(a630_rscc_snapshot_registers) / 2);

	} else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {

		adreno_snapshot_registers(device, snapshot,

			a6xx_rscc_snapshot_registers,

			ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2);

	}



	sptprac_on = gpudev->sptprac_is_on(adreno_dev);



	if (!gmu_core_dev_gx_is_on(device))
@@ -1545,15 +1657,6 @@ void a6xx_snapshot(struct adreno_device *adreno_dev, 
			snapshot, a6xx_snapshot_registers, &a6xx_reg_list[i]);

	}



	if (adreno_is_a615_family(adreno_dev) || adreno_is_a630(adreno_dev))

		adreno_snapshot_registers(device, snapshot,

			a630_rscc_snapshot_registers,

			ARRAY_SIZE(a630_rscc_snapshot_registers) / 2);

	else if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev))

		adreno_snapshot_registers(device, snapshot,

			a6xx_rscc_snapshot_registers,

			ARRAY_SIZE(a6xx_rscc_snapshot_registers) / 2);



	/* CP_SQE indexed registers */

	kgsl_snapshot_indexed_registers(device, snapshot,

		A6XX_CP_SQE_STAT_ADDR, A6XX_CP_SQE_STAT_DATA, 0, 0x33);