Merge "Revert "drm/msm/disp/dpu: Remove unused funcs in dpu_formats.c"" (e080168f) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c

+41 −0

Original line number	Diff line number	Diff line
		@@ -869,6 +869,47 @@ int dpu_format_get_plane_sizes(
		return _dpu_format_get_plane_sizes_linear(fmt, w, h, layout, pitches);
		}

		int dpu_format_get_block_size(const struct dpu_format *fmt,
		uint32_t w, uint32_t h)
		{
		if (!fmt \|\| !w \|\| !h) {
		DRM_ERROR("invalid pointer\n");
		return -EINVAL;
		}

		/* TP10 is 96x96 and all others are 128x128 */
		if (DPU_FORMAT_IS_YUV(fmt) && DPU_FORMAT_IS_DX(fmt) &&
		(fmt->num_planes == 2) && fmt->unpack_tight)
		w = h = 96;
		else
		w = h = 128;

		return 0;
		}

		uint32_t dpu_format_get_framebuffer_size(
		const uint32_t format,
		const uint32_t width,
		const uint32_t height,
		const uint32_t *pitches,
		const uint64_t modifiers)
		{
		const struct dpu_format *fmt;
		struct dpu_hw_fmt_layout layout;

		fmt = dpu_get_dpu_format_ext(format, modifiers);
		if (!fmt)
		return 0;

		if (!pitches)
		return -EINVAL;

		if (dpu_format_get_plane_sizes(fmt, width, height, &layout, pitches))
		layout.total_size = 0;

		return layout.total_size;
		}

		static int _dpu_format_populate_addrs_ubwc(
		struct msm_gem_address_space *aspace,
		struct drm_framebuffer *fb,

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h

+30 −0

Original line number	Diff line number	Diff line
		@@ -72,6 +72,18 @@ int dpu_format_get_plane_sizes(
		struct dpu_hw_fmt_layout *layout,
		const uint32_t *pitches);

		/**
		* dpu_format_get_block_size - get block size of given format when
		* operating in block mode
		* @fmt: pointer to dpu_format
		* @w: pointer to width of the block
		* @h: pointer to height of the block
		*
		* Return: 0 if success; error oode otherwise
		*/
		int dpu_format_get_block_size(const struct dpu_format *fmt,
		uint32_t w, uint32_t h);

		/**
		* dpu_format_check_modified_format - validate format and buffers for
		* dpu non-standard, i.e. modified format
		@@ -103,4 +115,22 @@ int dpu_format_populate_layout(
		struct drm_framebuffer *fb,
		struct dpu_hw_fmt_layout *fmtl);

		/**
		* dpu_format_get_framebuffer_size - get framebuffer memory size
		* @format: DRM pixel format
		* @width: pixel width
		* @height: pixel height
		* @pitches: array of size [DPU_MAX_PLANES] to populate
		* pitch for each plane
		* @modifiers: drm modifier
		*
		* Return: memory size required for frame buffer
		*/
		uint32_t dpu_format_get_framebuffer_size(
		const uint32_t format,
		const uint32_t width,
		const uint32_t height,
		const uint32_t *pitches,
		const uint64_t modifiers);

		#endif /_DPU_FORMATS_H /

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c

+84 −0

Original line number	Diff line number	Diff line
		@@ -92,6 +92,59 @@ u32 *dpu_hw_util_get_log_mask_ptr(void)
		return &dpu_hw_util_log_mask;
		}

		void dpu_set_scaler_v2(struct dpu_hw_scaler3_cfg *cfg,
		const struct dpu_drm_scaler_v2 *scale_v2)
		{
		int i;

		cfg->enable = scale_v2->enable;
		cfg->dir_en = scale_v2->dir_en;

		for (i = 0; i < DPU_MAX_PLANES; i++) {
		cfg->init_phase_x[i] = scale_v2->init_phase_x[i];
		cfg->phase_step_x[i] = scale_v2->phase_step_x[i];
		cfg->init_phase_y[i] = scale_v2->init_phase_y[i];
		cfg->phase_step_y[i] = scale_v2->phase_step_y[i];

		cfg->preload_x[i] = scale_v2->preload_x[i];
		cfg->preload_y[i] = scale_v2->preload_y[i];
		cfg->src_width[i] = scale_v2->src_width[i];
		cfg->src_height[i] = scale_v2->src_height[i];
		}

		cfg->dst_width = scale_v2->dst_width;
		cfg->dst_height = scale_v2->dst_height;

		cfg->y_rgb_filter_cfg = scale_v2->y_rgb_filter_cfg;
		cfg->uv_filter_cfg = scale_v2->uv_filter_cfg;
		cfg->alpha_filter_cfg = scale_v2->alpha_filter_cfg;
		cfg->blend_cfg = scale_v2->blend_cfg;

		cfg->lut_flag = scale_v2->lut_flag;
		cfg->dir_lut_idx = scale_v2->dir_lut_idx;
		cfg->y_rgb_cir_lut_idx = scale_v2->y_rgb_cir_lut_idx;
		cfg->uv_cir_lut_idx = scale_v2->uv_cir_lut_idx;
		cfg->y_rgb_sep_lut_idx = scale_v2->y_rgb_sep_lut_idx;
		cfg->uv_sep_lut_idx = scale_v2->uv_sep_lut_idx;

		cfg->de.enable = scale_v2->de.enable;
		cfg->de.sharpen_level1 = scale_v2->de.sharpen_level1;
		cfg->de.sharpen_level2 = scale_v2->de.sharpen_level2;
		cfg->de.clip = scale_v2->de.clip;
		cfg->de.limit = scale_v2->de.limit;
		cfg->de.thr_quiet = scale_v2->de.thr_quiet;
		cfg->de.thr_dieout = scale_v2->de.thr_dieout;
		cfg->de.thr_low = scale_v2->de.thr_low;
		cfg->de.thr_high = scale_v2->de.thr_high;
		cfg->de.prec_shift = scale_v2->de.prec_shift;

		for (i = 0; i < DPU_MAX_DE_CURVES; i++) {
		cfg->de.adjust_a[i] = scale_v2->de.adjust_a[i];
		cfg->de.adjust_b[i] = scale_v2->de.adjust_b[i];
		cfg->de.adjust_c[i] = scale_v2->de.adjust_c[i];
		}
		}

		static void _dpu_hw_setup_scaler3_lut(struct dpu_hw_blk_reg_map *c,
		struct dpu_hw_scaler3_cfg *scaler3_cfg, u32 offset)
		{
		@@ -366,3 +419,34 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
		DPU_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]);
		DPU_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]);
		}

		/**
		* _dpu_copy_formats - copy formats from src_list to dst_list
		* @dst_list: pointer to destination list where to copy formats
		* @dst_list_size: size of destination list
		* @dst_list_pos: starting position on the list where to copy formats
		* @src_list: pointer to source list where to copy formats from
		* @src_list_size: size of source list
		* Return: number of elements populated
		*/
		uint32_t dpu_copy_formats(
		struct dpu_format_extended *dst_list,
		uint32_t dst_list_size,
		uint32_t dst_list_pos,
		const struct dpu_format_extended *src_list,
		uint32_t src_list_size)
		{
		uint32_t cur_pos, i;

		if (!dst_list \|\| !src_list \|\| (dst_list_pos >= (dst_list_size - 1)))
		return 0;

		for (i = 0, cur_pos = dst_list_pos;
		(cur_pos < (dst_list_size - 1)) && (i < src_list_size)
		&& src_list[i].fourcc_format; ++i, ++cur_pos)
		dst_list[cur_pos] = src_list[i];

		dst_list[cur_pos].fourcc_format = 0;

		return i;
		}

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -333,6 +333,9 @@ int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);

		void *dpu_hw_util_get_dir(void);

		void dpu_set_scaler_v2(struct dpu_hw_scaler3_cfg *cfg,
		const struct dpu_drm_scaler_v2 *scale_v2);

		void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
		struct dpu_hw_scaler3_cfg *scaler3_cfg,
		u32 scaler_offset, u32 scaler_version,
		@@ -345,4 +348,11 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c,
		u32 csc_reg_off,
		struct dpu_csc_cfg *data, bool csc10);

		uint32_t dpu_copy_formats(
		struct dpu_format_extended *dst_list,
		uint32_t dst_list_size,
		uint32_t dst_list_pos,
		const struct dpu_format_extended *src_list,
		uint32_t src_list_size);

		#endif /* _DPU_HW_UTIL_H */