Commit e058c945 authored May 27, 2015 by Jim Bride Committed by Jani Nikula Jun 01, 2015

drm/i915/hsw: Fix workaround for server AUX channel clock divisor



According to the HSW b-spec we need to try clock divisors of 63
and 72, each 3 or more times, when attempting DP AUX channel
communication on a server chipset.  This actually wasn't happening
due to a short-circuit that only checked the DP_AUX_CH_CTL_DONE bit
in status rather than checking that the operation was done and
that DP_AUX_CH_CTL_TIME_OUT_ERROR was not set.

[v2] Implemented alternate solution suggested by Jani Nikula.

Cc: stable@vger.kernel.org
Signed-off-by: Jim Bride <jim.bride@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

parent c65b99f0

drivers/gpu/drm/i915/intel_dp.c

+2 −3

Original line number	Diff line number	Diff line
		@@ -880,10 +880,8 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
		DP_AUX_CH_CTL_RECEIVE_ERROR))
		continue;
		if (status & DP_AUX_CH_CTL_DONE)
		break;
		goto done;
		}
		if (status & DP_AUX_CH_CTL_DONE)
		break;
		}

		if ((status & DP_AUX_CH_CTL_DONE) == 0) {
		@@ -892,6 +890,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
		goto out;
		}

		done:
		/* Check for timeout or receive error.
		* Timeouts occur when the sink is not connected
		*/