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Commit e045c540 authored by Taniya Das's avatar Taniya Das
Browse files

ARM: dts: msm: Update camcc and videocc clock node for LITO 



Update the camera & video clock node to use the camera clock driver and
also update the camera & video GDSCs to use the regulator driver.

Change-Id: I41cf40ee080faf74dd27a3523db90643678f2955
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent e90b1296

arch/arm64/boot/dts/qcom/lito-gdsc.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -43,37 +43,37 @@ 


	/* CAM_CC GDSCs */

	bps_gdsc: qcom,gdsc@ad07004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad07004 0x4>;

		regulator-name = "bps_gdsc";

	};



	ipe_0_gdsc: qcom,gdsc@ad08004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad08004 0x4>;

		regulator-name = "ipe_0_gdsc";

	};



	ipe_1_gdsc: qcom,gdsc@ad09004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad09004 0x4>;

		regulator-name = "ipe_1_gdsc";

	};



	ife_0_gdsc: qcom,gdsc@ad0a004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0a004 0x4>;

		regulator-name = "ife_0_gdsc";

	};



	ife_1_gdsc: qcom,gdsc@ad0b004 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0b004 0x4>;

		regulator-name = "ife_1_gdsc";

	};



	titan_top_gdsc: qcom,gdsc@ad0c1c4 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xad0c1c4 0x4>;

		regulator-name = "titan_top_gdsc";

	};
@@ -129,19 +129,19 @@ 


	/* VIDEO_CC GDSCs */

	mvsc_gdsc: qcom,gdsc@ab00814 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xab00814 0x4>;

		regulator-name = "mvsc_gdsc";

	};



	mvs0_gdsc: qcom,gdsc@ab00874 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xab00874 0x4>;

		regulator-name = "mvs0_gdsc";

	};



	mvs1_gdsc: qcom,gdsc@ab008b4 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		reg = <0xab008b4 0x4>;

		regulator-name = "mvs1_gdsc";

	};

arch/arm64/boot/dts/qcom/lito.dtsi

+48 −16
Original line number Diff line number Diff line
@@ -837,7 +837,7 @@ 
		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-output-names = "chip_sleep_clk";

			clock-frequency = <32764>;

			clock-frequency = <32000>;

			#clock-cells = <0>;

		};

	};
@@ -870,7 +870,7 @@ 
		#clock-cells = <1>;

	};



	gcc: qcom,gcc {

	gcc: qcom,gcc@100000 {

		compatible = "qcom,gcc-lito", "syscon";

		reg = <0x100000 0x1f0000>;

		reg-names = "cc_base";
@@ -880,6 +880,29 @@ 
		#reset-cells = <1>;

	};



	camcc: qcom,camcc@ad00000 {

		compatible = "qcom,lito-camcc", "syscon";

		reg = <0xad00000 0x10000>;

		reg-names = "cc_base";

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_CAMERA_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	videocc: qcom,videocc {

		compatible = "qcom,lito-videocc", "syscon";

		reg = <0x0ab00000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_VIDEO_AHB_CLK>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";
@@ -1013,20 +1036,6 @@ 
		#reset-cells = <1>;

	};



	videocc: qcom,videocc {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	camcc: qcom,camcc {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";
@@ -1341,26 +1350,41 @@ 
};



&bps_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};



&ipe_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};



&ipe_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};



&ife_0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	status = "ok";

};



&ife_1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	status = "ok";

};



&titan_top_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_CAMERA_AHB_CLK>;

	status = "ok";

};
@@ -1381,14 +1405,22 @@ 
};



&mvsc_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	status = "ok";

};



&mvs0_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};



&mvs1_gdsc {

	clock-names = "ahb_clk";

	clocks = <&gcc GCC_VIDEO_AHB_CLK>;

	qcom,support-hw-trigger;

	status = "ok";

};