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Commit e03eb527 authored by Catalin Marinas's avatar Catalin Marinas Committed by Russell King
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[ARM] 2954/1: Allow D and I cache and branch prediction disabling for ARMv6 



Patch from Catalin Marinas

There is no reason to not allow these config options. They are useful when
the hardware has problems.

Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent bb77c03c

arch/arm/mm/Kconfig

+4 −4
Original line number Diff line number Diff line
@@ -370,21 +370,21 @@ config CPU_BIG_ENDIAN 


config CPU_ICACHE_DISABLE

	bool "Disable I-Cache"

	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020

	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6

	help

	  Say Y here to disable the processor instruction cache. Unless

	  you have a reason not to or are unsure, say N.



config CPU_DCACHE_DISABLE

	bool "Disable D-Cache"

	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020

	depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6

	help

	  Say Y here to disable the processor data cache. Unless

	  you have a reason not to or are unsure, say N.



config CPU_DCACHE_WRITETHROUGH

	bool "Force write through D-cache"

	depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020) && !CPU_DCACHE_DISABLE

	depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE

	default y if CPU_ARM925T

	help

	  Say Y here to use the data cache in writethrough mode. Unless you
@@ -399,7 +399,7 @@ config CPU_CACHE_ROUND_ROBIN 


config CPU_BPREDICT_DISABLE

	bool "Disable branch prediction"

	depends on CPU_ARM1020

	depends on CPU_ARM1020 || CPU_V6

	help

	  Say Y here to disable branch prediction.  If unsure, say N.