msm: vidc: Change watchdog interrupt status and mask to 0x8

Watchdog Timer interrupt is at Bit 3 of interrupt status register.
Also removed unused/deprecated register macros.

CRs-Fixed: 2384822
Change-Id: I6a5b3f318edffac9ea1661b835bf0c300b5bd0be
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>