Loading drivers/sh/clk/core.c +3 −0 Original line number Diff line number Diff line Loading @@ -418,8 +418,11 @@ int clk_register(struct clk *clk) list_add(&clk->sibling, &root_clks); list_add(&clk->node, &clock_list); #ifdef CONFIG_SH_CLK_CPG_LEGACY if (clk->ops && clk->ops->init) clk->ops->init(clk); #endif out_unlock: mutex_unlock(&clock_list_sem); Loading drivers/sh/clk/cpg.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk) unsigned long value; int ret; ret = sh_clk_div6_set_rate(clk, clk->rate, 0); ret = sh_clk_div6_set_rate(clk, clk->rate); if (ret == 0) { value = __raw_readl(clk->enable_reg); value &= ~0x100; /* clear stop bit to enable clock */ Loading Loading
drivers/sh/clk/core.c +3 −0 Original line number Diff line number Diff line Loading @@ -418,8 +418,11 @@ int clk_register(struct clk *clk) list_add(&clk->sibling, &root_clks); list_add(&clk->node, &clock_list); #ifdef CONFIG_SH_CLK_CPG_LEGACY if (clk->ops && clk->ops->init) clk->ops->init(clk); #endif out_unlock: mutex_unlock(&clock_list_sem); Loading
drivers/sh/clk/cpg.c +1 −1 Original line number Diff line number Diff line Loading @@ -131,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk) unsigned long value; int ret; ret = sh_clk_div6_set_rate(clk, clk->rate, 0); ret = sh_clk_div6_set_rate(clk, clk->rate); if (ret == 0) { value = __raw_readl(clk->enable_reg); value &= ~0x100; /* clear stop bit to enable clock */ Loading