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Commit df849ba3 authored by Yang Shi's avatar Yang Shi Committed by David S. Miller
Browse files

arm64: bpf: add 'store immediate' instruction 



aarch64 doesn't have native store immediate instruction, such operation
has to be implemented by the below instruction sequence:

Load immediate to register
Store register

Signed-off-by: default avatarYang Shi <yang.shi@linaro.org>
CC: Zi Shen Lim <zlim.lnx@gmail.com>
CC: Xi Wang <xi.wang@gmail.com>
Reviewed-by: default avatarZi Shen Lim <zlim.lnx@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6bd4f355

arch/arm64/net/bpf_jit_comp.c

+19 −1
Original line number Original line Diff line number Diff line
@@ -590,7 +590,25 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 
	case BPF_ST | BPF_MEM | BPF_H:

	case BPF_ST | BPF_MEM | BPF_H:

	case BPF_ST | BPF_MEM | BPF_B:

	case BPF_ST | BPF_MEM | BPF_B:

	case BPF_ST | BPF_MEM | BPF_DW:

	case BPF_ST | BPF_MEM | BPF_DW:

		goto notyet;

		/* Load imm to a register then store it */

		ctx->tmp_used = 1;

		emit_a64_mov_i(1, tmp2, off, ctx);

		emit_a64_mov_i(1, tmp, imm, ctx);

		switch (BPF_SIZE(code)) {

		case BPF_W:

			emit(A64_STR32(tmp, dst, tmp2), ctx);

			break;

		case BPF_H:

			emit(A64_STRH(tmp, dst, tmp2), ctx);

			break;

		case BPF_B:

			emit(A64_STRB(tmp, dst, tmp2), ctx);

			break;

		case BPF_DW:

			emit(A64_STR64(tmp, dst, tmp2), ctx);

			break;

		}

		break;





	/* STX: *(size *)(dst + off) = src */

	/* STX: *(size *)(dst + off) = src */

	case BPF_STX | BPF_MEM | BPF_W:

	case BPF_STX | BPF_MEM | BPF_W: