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Commit dee47183 authored by Olof Johansson's avatar Olof Johansson
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ARM: tegra: fuse: add bct strapping reading 



This is used by the memory setup code to pick the right memory
timing table, if needed.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 9a1086da

arch/arm/mach-tegra/fuse.c

+14 −0
Original line number Diff line number Diff line
@@ -35,6 +35,17 @@ int tegra_cpu_process_id; 
int tegra_core_process_id;

enum tegra_revision tegra_revision;



/* The BCT to use at boot is specified by board straps that can be read

 * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.

 */

int tegra_bct_strapping;



#define STRAP_OPT 0x008

#define GMI_AD0 (1 << 4)

#define GMI_AD1 (1 << 5)

#define RAM_ID_MASK (GMI_AD0 | GMI_AD1)

#define RAM_CODE_SHIFT 4



static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {

	[TEGRA_REVISION_UNKNOWN] = "unknown",

	[TEGRA_REVISION_A01]     = "A01",
@@ -93,6 +104,9 @@ void tegra_init_fuse(void) 
	reg = tegra_fuse_readl(FUSE_SPARE_BIT);

	tegra_core_process_id = (reg >> 12) & 3;



	reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);

	tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;



	tegra_revision = tegra_get_revision();



	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",

arch/arm/mach-tegra/fuse.h

+2 −0
Original line number Diff line number Diff line
@@ -40,6 +40,8 @@ extern int tegra_cpu_process_id; 
extern int tegra_core_process_id;

extern enum tegra_revision tegra_revision;



extern int tegra_bct_strapping;



unsigned long long tegra_chip_uid(void);

void tegra_init_fuse(void);