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Commit de6e9066 authored by Rob Clark's avatar Rob Clark Committed by Greg Kroah-Hartman
Browse files

drm/msm: Fix a5xx/a6xx timestamps 



[ Upstream commit 9fbd3088351b92e8c2cef6e37a39decb12a8d5bb ]

They were reading a counter that was configured to ALWAYS_COUNT (ie.
cycles that the GPU is doing something) rather than ALWAYS_ON.  This
isn't the thing that userspace is looking for.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Acked-by: default avatarJordan Crouse <jordan@cosmicpenguin.net>
Message-Id: <20210325012358.1759770-2-robdclark@gmail.com>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 9c5d5efa

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -1194,8 +1194,8 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) 


static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)

{

	*value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO,

		REG_A5XX_RBBM_PERFCTR_CP_0_HI);

	*value = gpu_read64(gpu, REG_A5XX_RBBM_ALWAYSON_COUNTER_LO,

		REG_A5XX_RBBM_ALWAYSON_COUNTER_HI);



	return 0;

}

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+2 −2
Original line number Diff line number Diff line
@@ -713,8 +713,8 @@ static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) 
	/* Force the GPU power on so we can read this register */

	a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);



	*value = gpu_read64(gpu, REG_A6XX_RBBM_PERFCTR_CP_0_LO,

		REG_A6XX_RBBM_PERFCTR_CP_0_HI);

	*value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,

		REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);



	a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);

	return 0;