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Commit dd8849c8 authored by Jesse Barnes's avatar Jesse Barnes Committed by Chris Wilson
Browse files

drm/i915: don't enable self-refresh on Ironlake 

We don't know how to enable it safely, especially as outputs turn on and
off.  When disabling LP1 we also need to make sure LP2 and 3 are already
disabled.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29173
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29082


Reported-by: default avatarChris Lord <chris@linux.intel.com>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 7839d956

drivers/gpu/drm/i915/i915_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -2206,9 +2206,17 @@ 
#define  WM1_LP_SR_EN		(1<<31)

#define  WM1_LP_LATENCY_SHIFT	24

#define  WM1_LP_LATENCY_MASK	(0x7f<<24)

#define  WM1_LP_FBC_LP1_MASK	(0xf<<20)

#define  WM1_LP_FBC_LP1_SHIFT	20

#define  WM1_LP_SR_MASK		(0x1ff<<8)

#define  WM1_LP_SR_SHIFT	8

#define  WM1_LP_CURSOR_MASK	(0x3f)

#define WM2_LP_ILK		0x4510c

#define  WM2_LP_EN		(1<<31)

#define WM3_LP_ILK		0x45110

#define  WM3_LP_EN		(1<<31)

#define WM1S_LP_ILK		0x45120

#define  WM1S_LP_EN		(1<<31)



/* Memory latency timer register */

#define MLTR_ILK		0x11222

drivers/gpu/drm/i915/intel_display.c

+4 −2
Original line number Diff line number Diff line
@@ -3382,8 +3382,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock, 
		reg_value = I915_READ(WM1_LP_ILK);

		reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |

			       WM1_LP_CURSOR_MASK);

		reg_value |= WM1_LP_SR_EN |

			     (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

		reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |

			     (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;



		I915_WRITE(WM1_LP_ILK, reg_value);
@@ -5669,6 +5668,9 @@ void intel_init_clock_gating(struct drm_device *dev) 
			I915_WRITE(DISP_ARB_CTL,

					(I915_READ(DISP_ARB_CTL) |

						DISP_FBC_WM_DIS));

		I915_WRITE(WM3_LP_ILK, 0);

		I915_WRITE(WM2_LP_ILK, 0);

		I915_WRITE(WM1_LP_ILK, 0);

		}

		/*

		 * Based on the document from hardware guys the following bits