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Commit dd259935 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

kvm: x86: move MSR_IA32_TSC handling to x86.c 



This is not specific to Intel/AMD anymore.  The TSC offset is available
in vcpu->arch.tsc_offset.

Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent e79f245d

arch/x86/kvm/svm.c

+0 −9
Original line number Diff line number Diff line
@@ -4050,12 +4050,6 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
	struct vcpu_svm *svm = to_svm(vcpu);



	switch (msr_info->index) {

	case MSR_IA32_TSC: {

		msr_info->data = svm->vmcb->control.tsc_offset +

			kvm_scale_tsc(vcpu, rdtsc());



		break;

	}

	case MSR_STAR:

		msr_info->data = svm->vmcb->save.star;

		break;
@@ -4208,9 +4202,6 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 
		svm->vmcb->save.g_pat = data;

		mark_dirty(svm->vmcb, VMCB_NPT);

		break;

	case MSR_IA32_TSC:

		kvm_write_tsc(vcpu, msr);

		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS))

arch/x86/kvm/vmx.c

+0 −20
Original line number Diff line number Diff line
@@ -2885,20 +2885,6 @@ static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 
	return vcpu->arch.tsc_offset;

}



/*

 * reads and returns guest's timestamp counter "register"

 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset

 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3

 */

static u64 guest_read_tsc(struct kvm_vcpu *vcpu)

{

	u64 host_tsc, tsc_offset;



	host_tsc = rdtsc();

	tsc_offset = vmcs_read64(TSC_OFFSET);

	return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;

}



/*

 * writes 'offset' into guest's timestamp counter offset register

 */
@@ -3529,9 +3515,6 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
#endif

	case MSR_EFER:

		return kvm_get_msr_common(vcpu, msr_info);

	case MSR_IA32_TSC:

		msr_info->data = guest_read_tsc(vcpu);

		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&
@@ -3651,9 +3634,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
			return 1;

		vmcs_write64(GUEST_BNDCFGS, data);

		break;

	case MSR_IA32_TSC:

		kvm_write_tsc(vcpu, msr_info);

		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&

arch/x86/kvm/x86.c

+6 −0
Original line number Diff line number Diff line
@@ -2364,6 +2364,9 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
			return 1;

		vcpu->arch.smbase = data;

		break;

	case MSR_IA32_TSC:

		kvm_write_tsc(vcpu, msr_info);

		break;

	case MSR_SMI_COUNT:

		if (!msr_info->host_initiated)

			return 1;
@@ -2607,6 +2610,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
	case MSR_IA32_UCODE_REV:

		msr_info->data = vcpu->arch.microcode_version;

		break;

	case MSR_IA32_TSC:

		msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset;

		break;

	case MSR_MTRRcap:

	case 0x200 ... 0x2ff:

		return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);