drm/nouveau/secboot/r370: implement support for booting LS SEC2 ucode

	.lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD,

};

static void

acr_r370_generate_sec2_bl_desc(const struct nvkm_acr *acr,

			       const struct ls_ucode_img *img, u64 wpr_addr,

			       void *_desc)

{

	const struct ls_ucode_img_desc *pdesc = &img->ucode_desc;

	const struct nvkm_sec2 *sec = acr->subdev->device->sec2;

	struct acr_r370_flcn_bl_desc *desc = _desc;

	u64 base, addr_code, addr_data;

	u32 addr_args;

	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;

	/* For some reason we should not add app_resident_code_offset here */

	addr_code = base;

	addr_data = base + pdesc->app_resident_data_offset;

	addr_args = sec->falcon->data.limit;

	addr_args -= NVKM_MSGQUEUE_CMDLINE_SIZE;

	desc->ctx_dma = FALCON_SEC2_DMAIDX_UCODE;

	desc->code_dma_base = u64_to_flcn64(addr_code);

	desc->non_sec_code_off = pdesc->app_resident_code_offset;

	desc->non_sec_code_size = pdesc->app_resident_code_size;

	desc->code_entry_point = pdesc->app_imem_entry;

	desc->data_dma_base = u64_to_flcn64(addr_data);

	desc->data_size = pdesc->app_resident_data_size;

	desc->argc = 1;

	/* args are stored at the beginning of EMEM */

	desc->argv = 0x01000000;

}

const struct acr_r352_ls_func

acr_r370_ls_sec2_func = {

	.load = acr_ls_ucode_load_sec2,

	.generate_bl_desc = acr_r370_generate_sec2_bl_desc,

	.bl_desc_size = sizeof(struct acr_r370_flcn_bl_desc),

	.post_run = acr_ls_sec2_post_run,

};

void

acr_r370_generate_hs_bl_desc(const struct hsf_load_header *hdr, void *_bl_desc,

			     u64 offset)

	.ls_fill_headers = acr_r367_ls_fill_headers,

	.ls_write_wpr = acr_r367_ls_write_wpr,

	.ls_func = {

		[NVKM_SECBOOT_FALCON_SEC2] = &acr_r370_ls_sec2_func,

		[NVKM_SECBOOT_FALCON_FECS] = &acr_r370_ls_fecs_func,

		[NVKM_SECBOOT_FALCON_GPCCS] = &acr_r370_ls_gpccs_func,

	},