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Commit dcc32b83 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next into drm-fixes 

* 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next:
  drm/nv40: fall back to paged dma object for the moment
  drm/nouveau: fix leak of gart mm node
  drm/nouveau: fix vram page mapping when crossing page table boundaries
  drm/nv17-nv40: Fix modesetting failure when pitch == 4096px (fdo bug 35901).
  drm/nouveau: don't create accel engine objects when noaccel=1
  drm/nvc0: recognise 0xdX chipsets as NV_C0
parents de52bcab 4cff3ce5

drivers/gpu/drm/nouveau/nouveau_hw.c

+2 −0
Original line number Diff line number Diff line
@@ -900,6 +900,7 @@ nv_save_state_ext(struct drm_device *dev, int head, 
	}

	/* NV11 and NV20 don't have this, they stop at 0x52. */

	if (nv_gf4_disp_arch(dev)) {

		rd_cio_state(dev, head, regp, NV_CIO_CRE_42);

		rd_cio_state(dev, head, regp, NV_CIO_CRE_53);

		rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
@@ -1003,6 +1004,7 @@ nv_load_state_ext(struct drm_device *dev, int head, 
			nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);

		}



		wr_cio_state(dev, head, regp, NV_CIO_CRE_42);

		wr_cio_state(dev, head, regp, NV_CIO_CRE_53);

		wr_cio_state(dev, head, regp, NV_CIO_CRE_54);

drivers/gpu/drm/nouveau/nouveau_mem.c

+3 −1
Original line number Diff line number Diff line
@@ -397,7 +397,7 @@ nouveau_mem_vram_init(struct drm_device *dev) 
		if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))

			dma_bits = 40;

	} else

	if (drm_pci_device_is_pcie(dev) &&

	if (0 && drm_pci_device_is_pcie(dev) &&

	    dev_priv->chipset  > 0x40 &&

	    dev_priv->chipset != 0x45) {

		if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
@@ -868,7 +868,9 @@ nouveau_gart_manager_del(struct ttm_mem_type_manager *man, 
		nouveau_vm_unmap(&node->tmp_vma);

		nouveau_vm_put(&node->tmp_vma);

	}



	mem->mm_node = NULL;

	kfree(node);

}



static int

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+1 −1
Original line number Diff line number Diff line
@@ -458,7 +458,7 @@ nouveau_sgdma_init(struct drm_device *dev) 
		dev_priv->gart_info.type = NOUVEAU_GART_HW;

		dev_priv->gart_info.func = &nv50_sgdma_backend;

	} else

	if (drm_pci_device_is_pcie(dev) &&

	if (0 && drm_pci_device_is_pcie(dev) &&

	    dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {

		if (nv44_graph_class(dev)) {

			dev_priv->gart_info.func = &nv44_sgdma_backend;

drivers/gpu/drm/nouveau/nouveau_state.c

+58 −56
Original line number Diff line number Diff line
@@ -371,6 +371,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->vram.flags_valid	= nv50_vram_flags_valid;

		break;

	case 0xC0:

	case 0xD0:

		engine->instmem.init		= nvc0_instmem_init;

		engine->instmem.takedown	= nvc0_instmem_takedown;

		engine->instmem.suspend		= nvc0_instmem_suspend;
@@ -563,6 +564,7 @@ nouveau_card_init(struct drm_device *dev) 
	if (ret)

		goto out_timer;



	if (!nouveau_noaccel) {

		switch (dev_priv->card_type) {

		case NV_04:

			nv04_graph_create(dev);
@@ -624,7 +626,6 @@ nouveau_card_init(struct drm_device *dev) 
		    (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))

			nv50_mpeg_create(dev);



	if (!nouveau_noaccel) {

		for (e = 0; e < NVOBJ_ENGINE_NR; e++) {

			if (dev_priv->eng[e]) {

				ret = dev_priv->eng[e]->init(dev, e);
@@ -922,6 +923,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) 
		dev_priv->card_type = NV_50;

		break;

	case 0xc0:

	case 0xd0:

		dev_priv->card_type = NV_C0;

		break;

	default:

drivers/gpu/drm/nouveau/nouveau_vm.c

+1 −0
Original line number Diff line number Diff line
@@ -58,6 +58,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) 
			num -= len;

			pte += len;

			if (unlikely(end >= max)) {

				phys += len << (bits + 12);

				pde++;

				pte = 0;

			}