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Commit dcaee01c authored by Rishabh Jain's avatar Rishabh Jain Committed by Gerrit - the friendly Code Review server
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msm: camera: ope: Dump debug registers in case of HW hang



Add support for dumping debug registers in case of HW
hang. This will help to identify the culprit module in
case of HW hang.

CRs-Fixed: 2628745
Change-Id: Ie978df9eee684de4718dfce2aa47cd941704ae0d
Signed-off-by: default avatarRishabh Jain <risjai@codeaurora.org>
parent 812586fe
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+4 −0
Original line number Diff line number Diff line
@@ -349,6 +349,10 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data)

	if (cam_ope_is_pending_request(ctx_data)) {
		CAM_DBG(CAM_OPE, "pending requests means, issue is with HW");
		hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd(
				hw_mgr->ope_dev_intf[i]->hw_priv,
				OPE_HW_DUMP_DEBUG,
				NULL, 0);
		task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work);
		if (!task) {
			CAM_ERR(CAM_OPE, "no empty task");
+22 −0
Original line number Diff line number Diff line
@@ -285,6 +285,16 @@ int cam_ope_deinit_hw(void *device_priv,
	return rc;
}

static int cam_ope_dev_process_dump_debug_reg(struct ope_hw *ope_hw)
{
	int rc = 0;

	rc = cam_ope_top_process(ope_hw, -1,
		OPE_HW_DUMP_DEBUG, NULL);

	return rc;
}

static int cam_ope_dev_process_reset(struct ope_hw *ope_hw, void *cmd_args)
{
	int rc = 0;
@@ -1529,6 +1539,15 @@ static int cam_ope_process_probe(struct ope_hw *ope_hw,
	return -EINVAL;
}

static int cam_ope_process_dump_debug_reg(struct ope_hw *ope_hw,
	bool hfi_en)
{
	if (!hfi_en)
		return cam_ope_dev_process_dump_debug_reg(ope_hw);

	return -EINVAL;
}

static int cam_ope_process_reset(struct ope_hw *ope_hw,
	void *cmd_args, bool hfi_en)
{
@@ -1670,6 +1689,9 @@ int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type,
		spin_unlock_irqrestore(&ope_dev->hw_lock, flags);
		}
		break;
	case OPE_HW_DUMP_DEBUG:
		rc = cam_ope_process_dump_debug_reg(ope_hw, hfi_en);
		break;
	default:
		break;
	}
+2 −1
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 */

#ifndef CAM_OPE_DEV_INTF_H
@@ -28,6 +28,7 @@
#define OPE_HW_SET_IRQ_CB  0xE
#define OPE_HW_CLK_DISABLE 0xF
#define OPE_HW_CLK_ENABLE  0x10
#define OPE_HW_DUMP_DEBUG  0x11

/**
 * struct cam_ope_dev_probe
+11 −1
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 */

#ifndef CAM_OPE_HW_H
@@ -49,6 +49,8 @@
#define OPE_WAIT_COMP_IDLE    0x4
#define OPE_WAIT_COMP_GEN_IRQ 0x8

#define OPE_MAX_DEBUG_REGISTER 30

struct cam_ope_common {
	uint32_t mode[CAM_FORMAT_MAX];
};
@@ -68,6 +70,9 @@ struct cam_ope_top_reg {
	uint32_t irq_cmd;
	uint32_t violation_status;
	uint32_t throttle_cnt_cfg;
	uint32_t debug_cfg;
	uint32_t num_debug_registers;
	struct cam_ope_debug_register *debug_regs;
};

struct cam_ope_top_reg_val {
@@ -103,6 +108,7 @@ struct cam_ope_top_reg_val {
	uint32_t fe_done;
	uint32_t ope_violation;
	uint32_t idle;
	uint32_t debug_cfg_val;
};

struct cam_ope_qos_reg {
@@ -375,6 +381,10 @@ struct cam_ope_bus_wr_reg_val {
	struct cam_ope_bus_wr_client_reg_val wr_clients[MAX_WR_CLIENTS];
};

struct cam_ope_debug_register {
	uint32_t offset;
};

struct ope_hw {
	struct cam_ope_top_reg        *top_reg;
	struct cam_ope_top_reg_val    *top_reg_val;
+35 −1
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
 */

#ifndef CAM_OPE_HW_100_H
@@ -42,6 +42,36 @@ enum cam_ope_bus_rd_unpacker_format {
	BUS_RD_VER1_PACKER_FMT_MAX                         = 0x13,
};

static struct cam_ope_debug_register ope_debug_regs[OPE_MAX_DEBUG_REGISTER] = {
	{
		.offset = 0xA0,
	},
	{
		.offset = 0xA4
	},
	{
		.offset = 0xA8,
	},
	{
		.offset = 0xAC,
	},
	{
		.offset = 0xB0,
	},
	{
		.offset = 0xB4,
	},
	{
		.offset = 0xB8,
	},
	{
		.offset = 0xBC,
	},
	{
		.offset = 0xD0,
	},
};

static struct cam_ope_top_reg ope_top_reg = {
	.offset              = 0x400,
	.hw_version          = 0x0,
@@ -56,6 +86,9 @@ static struct cam_ope_top_reg ope_top_reg = {
	.irq_cmd             = 0x24,
	.violation_status    = 0x28,
	.throttle_cnt_cfg    = 0x2C,
	.debug_cfg           = 0xDC,
	.num_debug_registers = 9,
	.debug_regs          = ope_debug_regs,
};

static struct cam_ope_top_reg_val ope_top_reg_val = {
@@ -75,6 +108,7 @@ static struct cam_ope_top_reg_val ope_top_reg_val = {
	.fe_done       = 0x4,
	.ope_violation = 0x8,
	.idle          = 0x10,
	.debug_cfg_val = 0x1,
};


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