Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dc81df24 authored by Vineet Gupta's avatar Vineet Gupta
Browse files

ARC: [tlb-miss] Fix bug with CONFIG_ARC_DBG_TLB_MISS_COUNT 



LOAD_FAULT_PTE macro is expected to set r2 with faulting vaddr.
However in case of CONFIG_ARC_DBG_TLB_MISS_COUNT, it was getting
clobbered with statistics collection code.

Fix latter by using a different register.

Note that only I-TLB Miss handler was potentially affected.

Signed-off-by: default avatarVineet Gupta <vgupta@synopsys.com>
parent c3e757a7

arch/arc/mm/tlbex.S

+5 −5
Original line number Diff line number Diff line
@@ -147,9 +147,9 @@ ex_saved_reg1: 
#ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT

	and.f 0, r0, _PAGE_PRESENT

	bz   1f

	ld   r2, [num_pte_not_present]

	add  r2, r2, 1

	st   r2, [num_pte_not_present]

	ld   r3, [num_pte_not_present]

	add  r3, r3, 1

	st   r3, [num_pte_not_present]

1:

#endif
@@ -271,7 +271,7 @@ ARC_ENTRY EV_TLBMissI 
#endif



	;----------------------------------------------------------------

	; Get the PTE corresponding to V-addr accessed

	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA

	LOAD_FAULT_PTE



	;----------------------------------------------------------------
@@ -311,7 +311,7 @@ ARC_ENTRY EV_TLBMissD 


	;----------------------------------------------------------------

	; Get the PTE corresponding to V-addr accessed

	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE

	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA

	LOAD_FAULT_PTE



	;----------------------------------------------------------------