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Commit dc4a1094 authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915: Pass pipe_config to fdi_link_train() functions 



It is preferred to pass pipe_config to functions instead of accessing
crtc->config directly. Follow suit and pass pipe_config to the fdi link
train functions.

v2: Add const; s/pipe_config/crtc_state/ (Ville)
Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170302125857.14665-5-ander.conselvan.de.oliveira@intel.com
parent 2ce42273

drivers/gpu/drm/i915/i915_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -669,7 +669,8 @@ struct drm_i915_display_funcs { 
				   struct intel_encoder *encoder,

				   const struct drm_display_mode *adjusted_mode);

	void (*audio_codec_disable)(struct intel_encoder *encoder);

	void (*fdi_link_train)(struct intel_crtc *crtc);

	void (*fdi_link_train)(struct intel_crtc *crtc,

			       const struct intel_crtc_state *crtc_state);

	void (*init_clock_gating)(struct drm_i915_private *dev_priv);

	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,

			  struct drm_framebuffer *fb,

drivers/gpu/drm/i915/intel_ddi.c

+5 −4
Original line number Diff line number Diff line
@@ -674,7 +674,8 @@ static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll) 
 * DDI A (which is used for eDP)

 */



void hsw_fdi_link_train(struct intel_crtc *crtc)

void hsw_fdi_link_train(struct intel_crtc *crtc,

			const struct intel_crtc_state *crtc_state)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -700,7 +701,7 @@ void hsw_fdi_link_train(struct intel_crtc *crtc) 
	/* Enable the PCH Receiver FDI PLL */

	rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |

		     FDI_RX_PLL_ENABLE |

		     FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes);

		     FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);

	POSTING_READ(FDI_RX_CTL(PIPE_A));

	udelay(220);
@@ -710,7 +711,7 @@ void hsw_fdi_link_train(struct intel_crtc *crtc) 
	I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);



	/* Configure Port Clock Select */

	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc->config->shared_dpll);

	ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);

	I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);

	WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
@@ -730,7 +731,7 @@ void hsw_fdi_link_train(struct intel_crtc *crtc) 
		 * port reversal bit */

		I915_WRITE(DDI_BUF_CTL(PORT_E),

			   DDI_BUF_CTL_ENABLE |

			   ((crtc->config->fdi_lanes - 1) << 1) |

			   ((crtc_state->fdi_lanes - 1) << 1) |

			   DDI_BUF_TRANS_SELECT(i / 2));

		POSTING_READ(DDI_BUF_CTL(PORT_E));

drivers/gpu/drm/i915/intel_display.c

+11 −8
Original line number Diff line number Diff line
@@ -3688,7 +3688,8 @@ static void intel_fdi_normal_train(struct intel_crtc *crtc) 
}



/* The FDI link training functions for ILK/Ibexpeak. */

static void ironlake_fdi_link_train(struct intel_crtc *crtc)

static void ironlake_fdi_link_train(struct intel_crtc *crtc,

				    const struct intel_crtc_state *crtc_state)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3713,7 +3714,7 @@ static void ironlake_fdi_link_train(struct intel_crtc *crtc) 
	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_DP_PORT_WIDTH_MASK;

	temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes);

	temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	I915_WRITE(reg, temp | FDI_TX_ENABLE);
@@ -3788,7 +3789,8 @@ static const int snb_b_fdi_train_param[] = { 
};



/* The FDI link training functions for SNB/Cougarpoint. */

static void gen6_fdi_link_train(struct intel_crtc *crtc)

static void gen6_fdi_link_train(struct intel_crtc *crtc,

				const struct intel_crtc_state *crtc_state)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3811,7 +3813,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc) 
	reg = FDI_TX_CTL(pipe);

	temp = I915_READ(reg);

	temp &= ~FDI_DP_PORT_WIDTH_MASK;

	temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes);

	temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

	temp &= ~FDI_LINK_TRAIN_NONE;

	temp |= FDI_LINK_TRAIN_PATTERN_1;

	temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
@@ -3920,7 +3922,8 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc) 
}



/* Manual link training for Ivy Bridge A0 parts */

static void ivb_manual_fdi_link_train(struct intel_crtc *crtc)

static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,

				      const struct intel_crtc_state *crtc_state)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3962,7 +3965,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc) 
		reg = FDI_TX_CTL(pipe);

		temp = I915_READ(reg);

		temp &= ~FDI_DP_PORT_WIDTH_MASK;

		temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes);

		temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);

		temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;

		temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;

		temp |= snb_b_fdi_train_param[j/2];
@@ -4474,7 +4477,7 @@ static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) 
		   I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);



	/* For PCH output, training FDI link */

	dev_priv->display.fdi_link_train(crtc);

	dev_priv->display.fdi_link_train(crtc, crtc_state);



	/* We need to program the right clock selection before writing the pixel

	 * mutliplier into the DPLL. */
@@ -5366,7 +5369,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, 
	intel_encoders_pre_enable(crtc, pipe_config, old_state);



	if (intel_crtc->config->has_pch_encoder)

		dev_priv->display.fdi_link_train(intel_crtc);

		dev_priv->display.fdi_link_train(intel_crtc, pipe_config);



	if (!transcoder_is_dsi(cpu_transcoder))

		intel_ddi_enable_pipe_clock(intel_crtc);

drivers/gpu/drm/i915/intel_drv.h

+2 −1
Original line number Diff line number Diff line
@@ -1225,7 +1225,8 @@ void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder, 
				struct intel_crtc_state *old_crtc_state,

				struct drm_connector_state *old_conn_state);

void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);

void hsw_fdi_link_train(struct intel_crtc *crtc);

void hsw_fdi_link_train(struct intel_crtc *crtc,

			const struct intel_crtc_state *crtc_state);

void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);

enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);

bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);