Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit dc2b2a91 authored by Mike Marciniszyn's avatar Mike Marciniszyn Committed by Jason Gunthorpe
Browse files

IB/hfi1: Add bypass register defines and replace blind constants 



These registers were not added in the 16B work.

Add them and replace blind constants with the correct defines.

Fixes: 72c07e2b ("IB/hfi1: Add support to receive 16B bypass packets")
Reviewed-by: default avatarDon Hiatt <don.hiatt@intel.com>
Signed-off-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 5465f110

drivers/infiniband/hw/hfi1/chip.c

+3 −1
Original line number Diff line number Diff line
@@ -14640,7 +14640,9 @@ static void init_rxe(struct hfi1_devdata *dd) 


	/* Have 16 bytes (4DW) of bypass header available in header queue */

	val = read_csr(dd, RCV_BYPASS);

	val |= (4ull << 16);

	val &= ~RCV_BYPASS_HDR_SIZE_SMASK;

	val |= ((4ull & RCV_BYPASS_HDR_SIZE_MASK) <<

		RCV_BYPASS_HDR_SIZE_SHIFT);

	write_csr(dd, RCV_BYPASS, val);

}

drivers/infiniband/hw/hfi1/chip_registers.h

+6 −0
Original line number Diff line number Diff line
@@ -638,6 +638,12 @@ 
#define RCV_BTH_QP_KDETH_QP_MASK 0xFFull

#define RCV_BTH_QP_KDETH_QP_SHIFT 16

#define RCV_BYPASS (RXE + 0x000000000038)

#define RCV_BYPASS_HDR_SIZE_SHIFT 16

#define RCV_BYPASS_HDR_SIZE_MASK 0x1Full

#define RCV_BYPASS_HDR_SIZE_SMASK 0x1F0000ull

#define RCV_BYPASS_BYPASS_CONTEXT_SHIFT 0

#define RCV_BYPASS_BYPASS_CONTEXT_MASK 0xFFull

#define RCV_BYPASS_BYPASS_CONTEXT_SMASK 0xFFull

#define RCV_CONTEXTS (RXE + 0x000000000010)

#define RCV_COUNTER_ARRAY32 (RXE + 0x000000000400)

#define RCV_COUNTER_ARRAY64 (RXE + 0x000000000500)