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Commit dbcc78be authored by Mike Frysinger's avatar Mike Frysinger Committed by Bryan Wu
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Blackfin arch: all our other ports call this SIZE rather than SPI_LEN 



Signed-off-by: default avatarMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent f0b5d12f

include/asm-blackfin/mach-bf533/defBF532.h

+1 −1
Original line number Diff line number Diff line
@@ -928,7 +928,7 @@ 
#define GM                     0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */

#define PSSE                   0x00000010	/* Enable (=1) Slave-Select input for Master. */

#define EMISO                  0x00000020	/* Enable (=1) MISO pin as an output. */

#define SPI_LEN                0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */

#define SIZE                   0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */

#define LSBF                   0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */

#define CPHA                   0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */

#define CPOL                   0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */

include/asm-blackfin/mach-bf537/defBF534.h

+1 −1
Original line number Diff line number Diff line
@@ -1165,7 +1165,7 @@ 
#define GM			0x0008	/* Get More (When RDBR Full, Overwrite/Discard*)        */

#define PSSE		0x0010	/* Slave-Select Input Enable                                            */

#define EMISO		0x0020	/* Enable MISO As Output                                                        */

#define SPI_SIZE	0x0100	/* Size of Words (16/8* Bits)                                           */

#define SIZE		0x0100	/* Size of Words (16/8* Bits)                                           */

#define LSBF		0x0200	/* LSB First                                                                            */

#define CPHA		0x0400	/* Clock Phase                                                                          */

#define CPOL		0x0800	/* Clock Polarity                                                                       */