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Commit db91f2e4 authored by Vivek Natarajan's avatar Vivek Natarajan Committed by John W. Linville
Browse files

ath9k: Add open loop power control support for AR9287. 



Signed-off-by: default avatarVivek Natarajan <vnatarajan@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 1e711bee

drivers/net/wireless/ath/ath9k/calib.c

+30 −14
Original line number Original line Diff line number Diff line
@@ -729,12 +729,27 @@ s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) 
static void ath9k_olc_temp_compensation(struct ath_hw *ah)

static void ath9k_olc_temp_compensation(struct ath_hw *ah)

{

{

	u32 rddata, i;

	u32 rddata, i;

	int delta, currPDADC, regval;

	int delta, currPDADC, regval, slope;





	rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);

	rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);



	currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);

	currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);







	if (OLC_FOR_AR9287_10_LATER) {

		if (ah->initPDADC == 0 || currPDADC == 0) {

			return;

		} else {

			slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);

			if (slope == 0)

				delta = 0;

			else

				delta = ((currPDADC - ah->initPDADC)*4) / slope;

			REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,

					AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);

			REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,

					AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);

		}

	} else {

		if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))

		if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))

			delta = (currPDADC - ah->initPDADC + 4) / 8;

			delta = (currPDADC - ah->initPDADC + 4) / 8;

		else

		else
@@ -752,6 +767,7 @@ static void ath9k_olc_temp_compensation(struct ath_hw *ah) 
			}

			}

		}

		}

	}

	}

}





static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)

static void ath9k_hw_9271_pa_cal(struct ath_hw *ah)

{

{

drivers/net/wireless/ath/ath9k/hw.c

+15 −5
Original line number Original line Diff line number Diff line
@@ -1332,12 +1332,22 @@ static void ath9k_olc_init(struct ath_hw *ah) 
{

{

	u32 i;

	u32 i;





	if (OLC_FOR_AR9287_10_LATER) {

		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,

				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);

		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,

				AR9287_AN_TXPC0_TXPCMODE,

				AR9287_AN_TXPC0_TXPCMODE_S,

				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);

		udelay(100);

	} else {

		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)

		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)

			ah->originalGain[i] =

			ah->originalGain[i] =

				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),

				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),

						AR_PHY_TX_GAIN);

						AR_PHY_TX_GAIN);

		ah->PDADCdelta = 0;

		ah->PDADCdelta = 0;

	}

	}

}





static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,

static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,

			      struct ath9k_channel *chan)

			      struct ath9k_channel *chan)

drivers/net/wireless/ath/ath9k/phy.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -490,11 +490,18 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, 
#define AR_PHY_TX_PWRCTRL9       0xa27C

#define AR_PHY_TX_PWRCTRL9       0xa27C

#define AR_PHY_TX_DESIRED_SCALE_CCK        0x00007C00

#define AR_PHY_TX_DESIRED_SCALE_CCK        0x00007C00

#define AR_PHY_TX_DESIRED_SCALE_CCK_S      10

#define AR_PHY_TX_DESIRED_SCALE_CCK_S      10

#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL  0x80000000

#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31





#define AR_PHY_TX_GAIN_TBL1      0xa300

#define AR_PHY_TX_GAIN_TBL1      0xa300

#define AR_PHY_TX_GAIN                     0x0007F000

#define AR_PHY_TX_GAIN                     0x0007F000

#define AR_PHY_TX_GAIN_S                   12

#define AR_PHY_TX_GAIN_S                   12





#define AR_PHY_CH0_TX_PWRCTRL11  0xa398

#define AR_PHY_CH1_TX_PWRCTRL11  0xb398

#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP   0x0000FC00

#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10



#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0

#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0

#define AR_PHY_MASK2_M_31_45     0xa3a4

#define AR_PHY_MASK2_M_31_45     0xa3a4

#define AR_PHY_MASK2_M_16_30     0xa3a8

#define AR_PHY_MASK2_M_16_30     0xa3a8