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Commit db8aa69b authored by Samantha Tran's avatar Samantha Tran
Browse files

drm/msm/sde:remove horz and vert decimation support for Kona 



This change adds the ability to disable decimation when
it is not supported. Setting decimation to true will default
it to the current maximum decimation supported by the targets.
If decimation property is not set, max horizontal and vertical
decimation will be set to 0.

Change-Id: Id26b32bba0707a7c24a1954568ad098d982674ce
Signed-off-by: default avatarSamantha Tran <samtran@codeaurora.org>
parent ab1f2fa2

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+14 −2
Original line number Diff line number Diff line
@@ -1431,8 +1431,13 @@ static int sde_sspp_parse_dt(struct device_node *np, 
			goto end;

		}



		if (sde_cfg->has_decimation) {

			sblk->maxhdeciexp = MAX_HORZ_DECIMATION;

			sblk->maxvdeciexp = MAX_VERT_DECIMATION;

		} else {

			sblk->maxhdeciexp = 0;

			sblk->maxvdeciexp = 0;

		}



		sspp->xin_id = PROP_VALUE_ACCESS(prop_value, SSPP_XIN, i);

		sblk->pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE;
@@ -3575,6 +3580,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->perf.min_prefill_lines = 21;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_MSM8998_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 25;
@@ -3582,6 +3588,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->ts_prefill_rev = 1;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_SDM845_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->has_cwb_support = true;
@@ -3592,6 +3599,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->sui_block_xin_mask = 0x3F71;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_SDM670_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 24;
@@ -3599,6 +3607,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->ts_prefill_rev = 2;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_SM8150_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_wb_ubwc = true;
@@ -3614,6 +3623,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_3d_merge_reset = true;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_SDMSHRIKE_TARGET(hw_rev)) {

		sde_cfg->has_wb_ubwc = true;

		sde_cfg->perf.min_prefill_lines = 24;
@@ -3623,6 +3633,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->delay_prg_fetch_start = true;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

		sde_cfg->has_decimation = true;

	} else if (IS_SM6150_TARGET(hw_rev)) {

		sde_cfg->has_cwb_support = true;

		sde_cfg->has_qsync = true;
@@ -3633,6 +3644,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->delay_prg_fetch_start = true;

		sde_cfg->sui_ns_allowed = true;

		sde_cfg->sui_misr_supported = true;

		sde_cfg->has_decimation = true;

		sde_cfg->sui_block_xin_mask = 0x2EE1;

		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);

		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1076,6 +1076,7 @@ struct sde_perf_cfg { 
 * @delay_prg_fetch_start indicates if throttling the fetch start is required

 * @has_qsync	       Supports qsync feature

 * @has_3d_merge_reset Supports 3D merge reset

 * @has_decimation     Supports decimation

 * @sui_misr_supported  indicate if secure-ui-misr is supported

 * @sui_block_xin_mask  mask of all the xin-clients to be blocked during

 *                         secure-ui when secure-ui-misr feature is supported
@@ -1123,6 +1124,7 @@ struct sde_mdss_cfg { 
	bool delay_prg_fetch_start;

	bool has_qsync;

	bool has_3d_merge_reset;

	bool has_decimation;



	bool sui_misr_supported;

	u32 sui_block_xin_mask;