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Commit db47ccce authored by Paul Walmsley's avatar Paul Walmsley
Browse files

Merge branches 'omap4_clockdomain_hwmod_3.1', 'clock_debugfs_a_3.1',... 

Merge branches 'omap4_clockdomain_hwmod_3.1', 'clock_debugfs_a_3.1', 'omap4_clock_auxclk_3.1' and 'omap_device_a_3.1' into prcm-devel-3.1
parents 665d0013 a5302572 ad03f1cb bf1e0776

arch/arm/mach-omap2/clock2420_data.c

+11 −11
Original line number Diff line number Diff line
@@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = { 
	CLK(NULL,	"gfx_ick",	&gfx_ick,	CK_242X),

	/* DSS domain clocks */

	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_242X),

	CLK("omapdss_dss",	"fck",		&dss1_fck,	CK_242X),

	CLK("omapdss_dss",	"sys_clk",	&dss2_fck,	CK_242X),

	CLK("omapdss_dss",	"tv_clk",	&dss_54m_fck,	CK_242X),

	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_242X),

	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_242X),

	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_242X),

	/* L3 domain clocks */

	CLK(NULL,	"core_l3_ck",	&core_l3_ck,	CK_242X),

	CLK(NULL,	"ssi_fck",	&ssi_ssr_sst_fck, CK_242X),
@@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = { 
	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_242X),

	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_242X),

	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_242X),

	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_242X),

	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_242X),

	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_242X),

	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_242X),

	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_242X),

	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_242X),

	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_242X),

	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_242X),

	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_242X),

	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_242X),

	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_242X),

	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_242X),

	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_242X),

	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_242X),
@@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = { 
	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_242X),

	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_242X),

	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_242X),

	CLK("omap_wdt",	"fck",		&mpu_wdt_fck,	CK_242X),

	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_242X),

	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_242X),

	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_242X),

	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_242X),
@@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = { 
	CLK(NULL,	"eac_ick",	&eac_ick,	CK_242X),

	CLK(NULL,	"eac_fck",	&eac_fck,	CK_242X),

	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_242X),

	CLK("omap_hdq.1", "fck",	&hdq_fck,	CK_242X),

	CLK("omap_hdq.0", "fck",	&hdq_fck,	CK_242X),

	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_242X),

	CLK("omap_i2c.1", "fck",	&i2c1_fck,	CK_242X),

	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_242X),

	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_242X),

	CLK("omap_i2c.2", "fck",	&i2c2_fck,	CK_242X),

	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_242X),

	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),

	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),

	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_242X),

arch/arm/mach-omap2/clock2430_data.c

+16 −16
Original line number Diff line number Diff line
@@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = { 
	CLK(NULL,	"mdm_osc_ck",	&mdm_osc_ck,	CK_243X),

	/* DSS domain clocks */

	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_243X),

	CLK("omapdss_dss",	"fck",		&dss1_fck,	CK_243X),

	CLK("omapdss_dss",	"sys_clk",	&dss2_fck,	CK_243X),

	CLK("omapdss_dss",	"tv_clk",	&dss_54m_fck,	CK_243X),

	CLK(NULL,	"dss1_fck",		&dss1_fck,	CK_243X),

	CLK(NULL,	"dss2_fck",	&dss2_fck,	CK_243X),

	CLK(NULL,	"dss_54m_fck",	&dss_54m_fck,	CK_243X),

	/* L3 domain clocks */

	CLK(NULL,	"core_l3_ck",	&core_l3_ck,	CK_243X),

	CLK(NULL,	"ssi_fck",	&ssi_ssr_sst_fck, CK_243X),
@@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = { 
	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_243X),

	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_243X),

	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_243X),

	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_243X),

	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_243X),

	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_243X),

	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_243X),

	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_243X),

	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_243X),

	CLK("omap-mcbsp.3", "fck",	&mcbsp3_fck,	CK_243X),

	CLK(NULL,	"mcbsp3_fck",	&mcbsp3_fck,	CK_243X),

	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_243X),

	CLK("omap-mcbsp.4", "fck",	&mcbsp4_fck,	CK_243X),

	CLK(NULL,	"mcbsp4_fck",	&mcbsp4_fck,	CK_243X),

	CLK("omap-mcbsp.5", "ick",	&mcbsp5_ick,	CK_243X),

	CLK("omap-mcbsp.5", "fck",	&mcbsp5_fck,	CK_243X),

	CLK(NULL,	"mcbsp5_fck",	&mcbsp5_fck,	CK_243X),

	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_243X),

	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_243X),

	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_243X),

	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_243X),

	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_243X),

	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_243X),

	CLK("omap2_mcspi.3", "ick",	&mcspi3_ick,	CK_243X),

	CLK("omap2_mcspi.3", "fck",	&mcspi3_fck,	CK_243X),

	CLK(NULL,	"mcspi3_fck",	&mcspi3_fck,	CK_243X),

	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_243X),

	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_243X),

	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_243X),
@@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = { 
	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_243X),

	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_243X),

	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_243X),

	CLK("omap_wdt",	"fck",		&mpu_wdt_fck,	CK_243X),

	CLK(NULL,	"mpu_wdt_fck",	&mpu_wdt_fck,	CK_243X),

	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_243X),

	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_243X),

	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_243X),
@@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = { 
	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_243X),

	CLK("omap_hdq.1", "fck",	&hdq_fck,	CK_243X),

	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_243X),

	CLK("omap_i2c.1", "fck",	&i2chs1_fck,	CK_243X),

	CLK(NULL,	"i2chs1_fck",	&i2chs1_fck,	CK_243X),

	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_243X),

	CLK("omap_i2c.2", "fck",	&i2chs2_fck,	CK_243X),

	CLK(NULL,	"i2chs2_fck",	&i2chs2_fck,	CK_243X),

	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_243X),

	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_243X),

	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_243X),
@@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = { 
	CLK(NULL,	"usb_fck",	&usb_fck,	CK_243X),

	CLK("musb-omap2430",	"ick",	&usbhs_ick,	CK_243X),

	CLK("omap_hsmmc.0", "ick",	&mmchs1_ick,	CK_243X),

	CLK("omap_hsmmc.0", "fck",	&mmchs1_fck,	CK_243X),

	CLK(NULL,	"mmchs1_fck",	&mmchs1_fck,	CK_243X),

	CLK("omap_hsmmc.1", "ick",	&mmchs2_ick,	CK_243X),

	CLK("omap_hsmmc.1", "fck",	&mmchs2_fck,	CK_243X),

	CLK(NULL,	"mmchs2_fck",	&mmchs2_fck,	CK_243X),

	CLK(NULL,	"gpio5_ick",	&gpio5_ick,	CK_243X),

	CLK(NULL,	"gpio5_fck",	&gpio5_fck,	CK_243X),

	CLK(NULL,	"mdm_intc_ick",	&mdm_intc_ick,	CK_243X),

arch/arm/mach-omap2/clock3xxx_data.c

+22 −22
Original line number Diff line number Diff line
@@ -3289,20 +3289,20 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK("omap-mcbsp.1",	"prcm_fck",	&core_96m_fck,	CK_3XXX),

	CLK("omap-mcbsp.5",	"prcm_fck",	&core_96m_fck,	CK_3XXX),

	CLK(NULL,	"core_96m_fck",	&core_96m_fck,	CK_3XXX),

	CLK("omap_hsmmc.2",	"fck",	&mmchs3_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),

	CLK("omap_hsmmc.1",	"fck",	&mmchs2_fck,	CK_3XXX),

	CLK(NULL,	"mmchs3_fck",	&mmchs3_fck,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),

	CLK(NULL,	"mmchs2_fck",	&mmchs2_fck,	CK_3XXX),

	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_34XX | CK_36XX),

	CLK("omap_hsmmc.0",	"fck",	&mmchs1_fck,	CK_3XXX),

	CLK("omap_i2c.3", "fck",	&i2c3_fck,	CK_3XXX),

	CLK("omap_i2c.2", "fck",	&i2c2_fck,	CK_3XXX),

	CLK("omap_i2c.1", "fck",	&i2c1_fck,	CK_3XXX),

	CLK("omap-mcbsp.5", "fck",	&mcbsp5_fck,	CK_3XXX),

	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_3XXX),

	CLK(NULL,	"mmchs1_fck",	&mmchs1_fck,	CK_3XXX),

	CLK(NULL,	"i2c3_fck",	&i2c3_fck,	CK_3XXX),

	CLK(NULL,	"i2c2_fck",	&i2c2_fck,	CK_3XXX),

	CLK(NULL,	"i2c1_fck",	&i2c1_fck,	CK_3XXX),

	CLK(NULL,	"mcbsp5_fck",	&mcbsp5_fck,	CK_3XXX),

	CLK(NULL,	"mcbsp1_fck",	&mcbsp1_fck,	CK_3XXX),

	CLK(NULL,	"core_48m_fck",	&core_48m_fck,	CK_3XXX),

	CLK("omap2_mcspi.4", "fck",	&mcspi4_fck,	CK_3XXX),

	CLK("omap2_mcspi.3", "fck",	&mcspi3_fck,	CK_3XXX),

	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_3XXX),

	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_3XXX),

	CLK(NULL,	"mcspi4_fck",	&mcspi4_fck,	CK_3XXX),

	CLK(NULL,	"mcspi3_fck",	&mcspi3_fck,	CK_3XXX),

	CLK(NULL,	"mcspi2_fck",	&mcspi2_fck,	CK_3XXX),

	CLK(NULL,	"mcspi1_fck",	&mcspi1_fck,	CK_3XXX),

	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_3XXX),

	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_3XXX),

	CLK(NULL,	"fshostusb_fck", &fshostusb_fck, CK_3430ES1),
@@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK("omap_rng",	"ick",		&rng_ick,	CK_34XX | CK_36XX),

	CLK(NULL,	"sha11_ick",	&sha11_ick,	CK_34XX | CK_36XX),

	CLK(NULL,	"des1_ick",	&des1_ick,	CK_34XX | CK_36XX),

	CLK("omapdss_dss",	"fck",		&dss1_alwon_fck_3430es1, CK_3430ES1),

	CLK("omapdss_dss",	"fck",		&dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),

	CLK("omapdss_dss",	"tv_clk",	&dss_tv_fck,	CK_3XXX),

	CLK("omapdss_dss",	"video_clk",	&dss_96m_fck,	CK_3XXX),

	CLK("omapdss_dss",	"sys_clk",	&dss2_alwon_fck, CK_3XXX),

	CLK(NULL,	"dss1_alwon_fck",		&dss1_alwon_fck_3430es1, CK_3430ES1),

	CLK(NULL,	"dss1_alwon_fck",		&dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),

	CLK(NULL,	"dss_tv_fck",	&dss_tv_fck,	CK_3XXX),

	CLK(NULL,	"dss_96m_fck",	&dss_96m_fck,	CK_3XXX),

	CLK(NULL,	"dss2_alwon_fck",	&dss2_alwon_fck, CK_3XXX),

	CLK("omapdss_dss",	"ick",		&dss_ick_3430es1,	CK_3430ES1),

	CLK("omapdss_dss",	"ick",		&dss_ick_3430es2,	CK_3430ES2PLUS | CK_AM35XX | CK_36XX),

	CLK(NULL,	"cam_mclk",	&cam_mclk,	CK_34XX | CK_36XX),
@@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_3XXX),

	CLK(NULL,	"wkup_32k_fck",	&wkup_32k_fck,	CK_3XXX),

	CLK(NULL,	"gpio1_dbck",	&gpio1_dbck,	CK_3XXX),

	CLK("omap_wdt",	"fck",		&wdt2_fck,	CK_3XXX),

	CLK(NULL,	"wdt2_fck",		&wdt2_fck,	CK_3XXX),

	CLK(NULL,	"wkup_l4_ick",	&wkup_l4_ick,	CK_34XX | CK_36XX),

	CLK(NULL,	"usim_ick",	&usim_ick,	CK_3430ES2PLUS | CK_36XX),

	CLK("omap_wdt",	"ick",		&wdt2_ick,	CK_3XXX),
@@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = { 
	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_3XXX),

	CLK("omap-mcbsp.3", "ick",	&mcbsp3_ick,	CK_3XXX),

	CLK("omap-mcbsp.4", "ick",	&mcbsp4_ick,	CK_3XXX),

	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_3XXX),

	CLK("omap-mcbsp.3", "fck",	&mcbsp3_fck,	CK_3XXX),

	CLK("omap-mcbsp.4", "fck",	&mcbsp4_fck,	CK_3XXX),

	CLK(NULL,	"mcbsp2_fck",	&mcbsp2_fck,	CK_3XXX),

	CLK(NULL,	"mcbsp3_fck",	&mcbsp3_fck,	CK_3XXX),

	CLK(NULL,	"mcbsp4_fck",	&mcbsp4_fck,	CK_3XXX),

	CLK("etb",	"emu_src_ck",	&emu_src_ck,	CK_3XXX),

	CLK(NULL,	"pclk_fck",	&pclk_fck,	CK_3XXX),

	CLK(NULL,	"pclkx2_fck",	&pclkx2_fck,	CK_3XXX),

arch/arm/mach-omap2/clock44xx_data.c

+171 −43
Original line number Diff line number Diff line
@@ -2774,19 +2774,39 @@ static struct clk trace_clk_div_ck = { 


/* SCRM aux clk nodes */



static const struct clksel auxclk_sel[] = {

static const struct clksel auxclk_src_sel[] = {

	{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },

	{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },

	{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },

	{ .parent = NULL },

};



static struct clk auxclk0_ck = {

	.name		= "auxclk0_ck",

static const struct clksel_rate div16_1to16_rates[] = {

	{ .div = 1, .val = 0, .flags = RATE_IN_4430 },

	{ .div = 2, .val = 1, .flags = RATE_IN_4430 },

	{ .div = 3, .val = 2, .flags = RATE_IN_4430 },

	{ .div = 4, .val = 3, .flags = RATE_IN_4430 },

	{ .div = 5, .val = 4, .flags = RATE_IN_4430 },

	{ .div = 6, .val = 5, .flags = RATE_IN_4430 },

	{ .div = 7, .val = 6, .flags = RATE_IN_4430 },

	{ .div = 8, .val = 7, .flags = RATE_IN_4430 },

	{ .div = 9, .val = 8, .flags = RATE_IN_4430 },

	{ .div = 10, .val = 9, .flags = RATE_IN_4430 },

	{ .div = 11, .val = 10, .flags = RATE_IN_4430 },

	{ .div = 12, .val = 11, .flags = RATE_IN_4430 },

	{ .div = 13, .val = 12, .flags = RATE_IN_4430 },

	{ .div = 14, .val = 13, .flags = RATE_IN_4430 },

	{ .div = 15, .val = 14, .flags = RATE_IN_4430 },

	{ .div = 16, .val = 15, .flags = RATE_IN_4430 },

	{ .div = 0 },

};



static struct clk auxclk0_src_ck = {

	.name		= "auxclk0_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK0,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2794,12 +2814,29 @@ static struct clk auxclk0_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static struct clk auxclk1_ck = {

	.name		= "auxclk1_ck",

static const struct clksel auxclk0_sel[] = {

	{ .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk0_ck = {

	.name		= "auxclk0_ck",

	.parent		= &auxclk0_src_ck,

	.clksel		= auxclk0_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK0,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static struct clk auxclk1_src_ck = {

	.name		= "auxclk1_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK1,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2807,12 +2844,29 @@ static struct clk auxclk1_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static struct clk auxclk2_ck = {

	.name		= "auxclk2_ck",

static const struct clksel auxclk1_sel[] = {

	{ .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk1_ck = {

	.name		= "auxclk1_ck",

	.parent		= &auxclk1_src_ck,

	.clksel		= auxclk1_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK1,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static struct clk auxclk2_src_ck = {

	.name		= "auxclk2_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK2,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2820,12 +2874,29 @@ static struct clk auxclk2_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static struct clk auxclk3_ck = {

	.name		= "auxclk3_ck",

static const struct clksel auxclk2_sel[] = {

	{ .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk2_ck = {

	.name		= "auxclk2_ck",

	.parent		= &auxclk2_src_ck,

	.clksel		= auxclk2_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK2,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static struct clk auxclk3_src_ck = {

	.name		= "auxclk3_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK3,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2833,12 +2904,29 @@ static struct clk auxclk3_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static struct clk auxclk4_ck = {

	.name		= "auxclk4_ck",

static const struct clksel auxclk3_sel[] = {

	{ .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk3_ck = {

	.name		= "auxclk3_ck",

	.parent		= &auxclk3_src_ck,

	.clksel		= auxclk3_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK3,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static struct clk auxclk4_src_ck = {

	.name		= "auxclk4_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK4,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2846,12 +2934,29 @@ static struct clk auxclk4_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static struct clk auxclk5_ck = {

	.name		= "auxclk5_ck",

static const struct clksel auxclk4_sel[] = {

	{ .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk4_ck = {

	.name		= "auxclk4_ck",

	.parent		= &auxclk4_src_ck,

	.clksel		= auxclk4_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK4,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static struct clk auxclk5_src_ck = {

	.name		= "auxclk5_src_ck",

	.parent		= &sys_clkin_ck,

	.init		= &omap2_init_clksel_parent,

	.ops		= &clkops_omap2_dflt,

	.clksel		= auxclk_sel,

	.clksel		= auxclk_src_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK5,

	.clksel_mask	= OMAP4_SRCSELECT_MASK,

	.recalc		= &omap2_clksel_recalc,
@@ -2859,6 +2964,23 @@ static struct clk auxclk5_ck = { 
	.enable_bit	= OMAP4_ENABLE_SHIFT,

};



static const struct clksel auxclk5_sel[] = {

	{ .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },

	{ .parent = NULL },

};



static struct clk auxclk5_ck = {

	.name		= "auxclk5_ck",

	.parent		= &auxclk5_src_ck,

	.clksel		= auxclk5_sel,

	.clksel_reg	= OMAP4_SCRM_AUXCLK5,

	.clksel_mask	= OMAP4_CLKDIV_MASK,

	.ops		= &clkops_null,

	.recalc		= &omap2_clksel_recalc,

	.round_rate	= &omap2_clksel_round_rate,

	.set_rate	= &omap2_clksel_set_rate,

};



static const struct clksel auxclkreq_sel[] = {

	{ .parent = &auxclk0_ck, .rates = div_1_0_rates },

	{ .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3057,12 +3179,12 @@ static struct omap_clk omap44xx_clks[] = { 
	CLK(NULL,	"gpio6_ick",			&gpio6_ick,	CK_443X),

	CLK(NULL,	"gpmc_ick",			&gpmc_ick,	CK_443X),

	CLK(NULL,	"gpu_fck",			&gpu_fck,	CK_443X),

	CLK("omap2_hdq.0",	"fck",				&hdq1w_fck,	CK_443X),

	CLK(NULL,	"hdq1w_fck",			&hdq1w_fck,	CK_443X),

	CLK(NULL,	"hsi_fck",			&hsi_fck,	CK_443X),

	CLK("omap_i2c.1",	"fck",				&i2c1_fck,	CK_443X),

	CLK("omap_i2c.2",	"fck",				&i2c2_fck,	CK_443X),

	CLK("omap_i2c.3",	"fck",				&i2c3_fck,	CK_443X),

	CLK("omap_i2c.4",	"fck",				&i2c4_fck,	CK_443X),

	CLK(NULL,	"i2c1_fck",			&i2c1_fck,	CK_443X),

	CLK(NULL,	"i2c2_fck",			&i2c2_fck,	CK_443X),

	CLK(NULL,	"i2c3_fck",			&i2c3_fck,	CK_443X),

	CLK(NULL,	"i2c4_fck",			&i2c4_fck,	CK_443X),

	CLK(NULL,	"ipu_fck",			&ipu_fck,	CK_443X),

	CLK(NULL,	"iss_ctrlclk",			&iss_ctrlclk,	CK_443X),

	CLK(NULL,	"iss_fck",			&iss_fck,	CK_443X),
@@ -3073,23 +3195,23 @@ static struct omap_clk omap44xx_clks[] = { 
	CLK(NULL,	"mcasp_sync_mux_ck",		&mcasp_sync_mux_ck,	CK_443X),

	CLK(NULL,	"mcasp_fck",			&mcasp_fck,	CK_443X),

	CLK(NULL,	"mcbsp1_sync_mux_ck",		&mcbsp1_sync_mux_ck,	CK_443X),

	CLK("omap-mcbsp.1",	"fck",				&mcbsp1_fck,	CK_443X),

	CLK(NULL,	"mcbsp1_fck",			&mcbsp1_fck,	CK_443X),

	CLK(NULL,	"mcbsp2_sync_mux_ck",		&mcbsp2_sync_mux_ck,	CK_443X),

	CLK("omap-mcbsp.2",	"fck",				&mcbsp2_fck,	CK_443X),

	CLK(NULL,	"mcbsp2_fck",			&mcbsp2_fck,	CK_443X),

	CLK(NULL,	"mcbsp3_sync_mux_ck",		&mcbsp3_sync_mux_ck,	CK_443X),

	CLK("omap-mcbsp.3",	"fck",				&mcbsp3_fck,	CK_443X),

	CLK(NULL,	"mcbsp3_fck",			&mcbsp3_fck,	CK_443X),

	CLK(NULL,	"mcbsp4_sync_mux_ck",		&mcbsp4_sync_mux_ck,	CK_443X),

	CLK("omap-mcbsp.4",	"fck",				&mcbsp4_fck,	CK_443X),

	CLK(NULL,	"mcbsp4_fck",			&mcbsp4_fck,	CK_443X),

	CLK(NULL,	"mcpdm_fck",			&mcpdm_fck,	CK_443X),

	CLK("omap2_mcspi.1",	"fck",				&mcspi1_fck,	CK_443X),

	CLK("omap2_mcspi.2",	"fck",				&mcspi2_fck,	CK_443X),

	CLK("omap2_mcspi.3",	"fck",				&mcspi3_fck,	CK_443X),

	CLK("omap2_mcspi.4",	"fck",				&mcspi4_fck,	CK_443X),

	CLK("omap_hsmmc.0",	"fck",				&mmc1_fck,	CK_443X),

	CLK("omap_hsmmc.1",	"fck",				&mmc2_fck,	CK_443X),

	CLK("omap_hsmmc.2",	"fck",				&mmc3_fck,	CK_443X),

	CLK("omap_hsmmc.3",	"fck",				&mmc4_fck,	CK_443X),

	CLK("omap_hsmmc.4",	"fck",				&mmc5_fck,	CK_443X),

	CLK(NULL,	"mcspi1_fck",			&mcspi1_fck,	CK_443X),

	CLK(NULL,	"mcspi2_fck",			&mcspi2_fck,	CK_443X),

	CLK(NULL,	"mcspi3_fck",			&mcspi3_fck,	CK_443X),

	CLK(NULL,	"mcspi4_fck",			&mcspi4_fck,	CK_443X),

	CLK(NULL,	"mmc1_fck",			&mmc1_fck,	CK_443X),

	CLK(NULL,	"mmc2_fck",			&mmc2_fck,	CK_443X),

	CLK(NULL,	"mmc3_fck",			&mmc3_fck,	CK_443X),

	CLK(NULL,	"mmc4_fck",			&mmc4_fck,	CK_443X),

	CLK(NULL,	"mmc5_fck",			&mmc5_fck,	CK_443X),

	CLK(NULL,	"ocp2scp_usb_phy_phy_48m",	&ocp2scp_usb_phy_phy_48m,	CK_443X),

	CLK(NULL,	"ocp2scp_usb_phy_ick",		&ocp2scp_usb_phy_ick,	CK_443X),

	CLK(NULL,	"ocp_wp_noc_ick",		&ocp_wp_noc_ick,	CK_443X),
@@ -3146,21 +3268,27 @@ static struct omap_clk omap44xx_clks[] = { 
	CLK(NULL,	"usim_ck",			&usim_ck,	CK_443X),

	CLK(NULL,	"usim_fclk",			&usim_fclk,	CK_443X),

	CLK(NULL,	"usim_fck",			&usim_fck,	CK_443X),

	CLK("omap_wdt",	"fck",				&wd_timer2_fck,	CK_443X),

	CLK(NULL,	"wd_timer2_fck",		&wd_timer2_fck,	CK_443X),

	CLK(NULL,	"wd_timer3_fck",		&wd_timer3_fck,	CK_443X),

	CLK(NULL,	"stm_clk_div_ck",		&stm_clk_div_ck,	CK_443X),

	CLK(NULL,	"trace_clk_div_ck",		&trace_clk_div_ck,	CK_443X),

	CLK(NULL,	"auxclk0_src_ck",		&auxclk0_src_ck,	CK_443X),

	CLK(NULL,	"auxclk0_ck",			&auxclk0_ck,	CK_443X),

	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck,	CK_443X),

	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck,	CK_443X),

	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck,	CK_443X),

	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck,	CK_443X),

	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck,	CK_443X),

	CLK(NULL,	"auxclkreq0_ck",		&auxclkreq0_ck,	CK_443X),

	CLK(NULL,	"auxclk1_src_ck",		&auxclk1_src_ck,	CK_443X),

	CLK(NULL,	"auxclk1_ck",			&auxclk1_ck,	CK_443X),

	CLK(NULL,	"auxclkreq1_ck",		&auxclkreq1_ck,	CK_443X),

	CLK(NULL,	"auxclk2_src_ck",		&auxclk2_src_ck,	CK_443X),

	CLK(NULL,	"auxclk2_ck",			&auxclk2_ck,	CK_443X),

	CLK(NULL,	"auxclkreq2_ck",		&auxclkreq2_ck,	CK_443X),

	CLK(NULL,	"auxclk3_src_ck",		&auxclk3_src_ck,	CK_443X),

	CLK(NULL,	"auxclk3_ck",			&auxclk3_ck,	CK_443X),

	CLK(NULL,	"auxclkreq3_ck",		&auxclkreq3_ck,	CK_443X),

	CLK(NULL,	"auxclk4_src_ck",		&auxclk4_src_ck,	CK_443X),

	CLK(NULL,	"auxclk4_ck",			&auxclk4_ck,	CK_443X),

	CLK(NULL,	"auxclkreq4_ck",		&auxclkreq4_ck,	CK_443X),

	CLK(NULL,	"auxclk5_src_ck",		&auxclk5_src_ck,	CK_443X),

	CLK(NULL,	"auxclk5_ck",			&auxclk5_ck,	CK_443X),

	CLK(NULL,	"auxclkreq5_ck",		&auxclkreq5_ck,	CK_443X),

	CLK(NULL,	"gpmc_ck",			&dummy_ck,	CK_443X),

	CLK(NULL,	"gpt1_ick",			&dummy_ck,	CK_443X),

arch/arm/plat-omap/clock.c

+39 −0
Original line number Diff line number Diff line
@@ -475,8 +475,41 @@ int __init clk_init(struct clk_functions * custom_clocks) 
/*

 *	debugfs support to trace clock tree hierarchy and attributes

 */



#include <linux/debugfs.h>

#include <linux/seq_file.h>



static struct dentry *clk_debugfs_root;



static int clk_dbg_show_summary(struct seq_file *s, void *unused)

{

	struct clk *c;

	struct clk *pa;



	seq_printf(s, "%-30s %-30s %-10s %s\n",

		"clock-name", "parent-name", "rate", "use-count");



	list_for_each_entry(c, &clocks, node) {

		pa = c->parent;

		seq_printf(s, "%-30s %-30s %-10lu %d\n",

			c->name, pa ? pa->name : "none", c->rate, c->usecount);

	}



	return 0;

}



static int clk_dbg_open(struct inode *inode, struct file *file)

{

	return single_open(file, clk_dbg_show_summary, inode->i_private);

}



static const struct file_operations debug_clock_fops = {

	.open           = clk_dbg_open,

	.read           = seq_read,

	.llseek         = seq_lseek,

	.release        = single_release,

};



static int clk_debugfs_register_one(struct clk *c)

{

	int err;
@@ -551,6 +584,12 @@ static int __init clk_debugfs_init(void) 
		if (err)

			goto err_out;

	}



	d = debugfs_create_file("summary", S_IRUGO,

		d, NULL, &debug_clock_fops);

	if (!d)

		return -ENOMEM;



	return 0;

err_out:

	debugfs_remove_recursive(clk_debugfs_root);