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Commit db020be9 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:

 - Consolidation of softirq pending:

   The softirq mask and its accessors/mutators have many implementations
   scattered around many architectures. Most do the same things
   consisting in a field in a per-cpu struct (often irq_cpustat_t)
   accessed through per-cpu ops. We can provide instead a generic
   efficient version that most of them can use. In fact s390 is the only
   exception because the field is stored in lowcore.

 - Support for level!?! triggered MSI (ARM)

   Over the past couple of years, we've seen some SoCs coming up with
   ways of signalling level interrupts using a new flavor of MSIs, where
   the MSI controller uses two distinct messages: one that raises a
   virtual line, and one that lowers it. The target MSI controller is in
   charge of maintaining the state of the line.

   This allows for a much simplified HW signal routing (no need to have
   hundreds of discrete lines to signal level interrupts if you already
   have a memory bus), but results in a departure from the current idea
   the kernel has of MSIs.

 - Support for Meson-AXG GPIO irqchip

 - Large stm32 irqchip rework (suspend/resume, hierarchical domains)

 - More SPDX conversions

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (36 commits)
  ARM: dts: stm32: Add exti support to stm32mp157 pinctrl
  ARM: dts: stm32: Add exti support for stm32mp157c
  pinctrl/stm32: Add irq_eoi for stm32gpio irqchip
  irqchip/stm32: Add suspend/resume support for hierarchy domain
  irqchip/stm32: Add stm32mp1 support with hierarchy domain
  irqchip/stm32: Prepare common functions
  irqchip/stm32: Add host and driver data structures
  irqchip/stm32: Add suspend support
  irqchip/stm32: Add falling pending register support
  irqchip/stm32: Checkpatch fix
  irqchip/stm32: Optimizes and cleans up stm32-exti irq_domain
  irqchip/meson-gpio: Add support for Meson-AXG SoCs
  dt-bindings: interrupt-controller: New binding for Meson-AXG SoC
  dt-bindings: interrupt-controller: Fix the double quotes
  softirq/s390: Move default mutators of overwritten softirq mask to s390
  softirq/x86: Switch to generic local_softirq_pending() implementation
  softirq/sparc: Switch to generic local_softirq_pending() implementation
  softirq/powerpc: Switch to generic local_softirq_pending() implementation
  softirq/parisc: Switch to generic local_softirq_pending() implementation
  softirq/ia64: Switch to generic local_softirq_pending() implementation
  ...
parents d09a8e6f 65441ba9

Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt

+6 −5
Original line number Diff line number Diff line
@@ -9,11 +9,12 @@ number of interrupt exposed depends on the SoC. 


Required properties:



- compatible : must have "amlogic,meson8-gpio-intc” and either

   “amlogic,meson8-gpio-intc” for meson8 SoCs (S802) or

   “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or

   “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or

   “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912)

- compatible : must have "amlogic,meson8-gpio-intc" and either

    "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or

    "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or

    "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or

    "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)

    "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)

- interrupt-parent : a phandle to the GIC the interrupts are routed to.

   Usually this is provided at the root level of the device tree as it is

   common to most of the SoC.

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

+17 −0
Original line number Diff line number Diff line
@@ -57,6 +57,20 @@ Optional 
  occupied by the redistributors. Required if more than one such

  region is present.



- msi-controller: Boolean property. Identifies the node as an MSI

  controller. Only present if the Message Based Interrupt

  functionnality is being exposed by the HW, and the mbi-ranges

  property present.



- mbi-ranges: A list of pairs <intid span>, where "intid" is the first

  SPI of a range that can be used an MBI, and "span" the size of that

  range. Multiple ranges can be provided. Requires "msi-controller" to

  be set.



- mbi-alias: Address property. Base address of an alias of the GICD

  region containing only the {SET,CLR}SPI registers to be used if

  isolation is required, and if supported by the HW.



Sub-nodes:



PPI affinity can be expressed as a single "ppi-partitions" node,
@@ -99,6 +113,9 @@ Examples: 
		      <0x0 0x2c020000 0 0x2000>;	// GICV

		interrupts = <1 9 4>;



		msi-controller;

		mbi-ranges = <256 128>;



		gic-its@2c200000 {

			compatible = "arm,gic-v3-its";

			msi-controller;

Documentation/devicetree/bindings/interrupt-controller/st,stm32-exti.txt

+3 −0
Original line number Diff line number Diff line
@@ -5,11 +5,14 @@ Required properties: 
- compatible: Should be:

    "st,stm32-exti"

    "st,stm32h7-exti"

    "st,stm32mp1-exti"

- reg: Specifies base physical address and size of the registers

- interrupt-controller: Indentifies the node as an interrupt controller

- #interrupt-cells: Specifies the number of cells to encode an interrupt

  specifier, shall be 2

- interrupts: interrupts references to primary interrupt controller

  (only needed for exti controller with multiple exti under

  same parent interrupt: st,stm32-exti and st,stm32h7-exti")



Example:

arch/arm/boot/dts/stm32mp157-pinctrl.dtsi

+4 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ 
			#size-cells = <1>;

			compatible = "st,stm32mp157-pinctrl";

			ranges = <0 0x50002000 0xa400>;

			interrupt-parent = <&exti>;

			st,syscfg = <&exti 0x60 0xff>;

			pins-are-numbered;



			gpioa: gpio@50002000 {
@@ -166,6 +168,8 @@ 
			compatible = "st,stm32mp157-z-pinctrl";

			ranges = <0 0x54004000 0x400>;

			pins-are-numbered;

			interrupt-parent = <&exti>;

			st,syscfg = <&exti 0x60 0xff>;

			status = "disabled";



			gpioz: gpio@54004000 {

arch/arm/boot/dts/stm32mp157c.dtsi

+7 −0
Original line number Diff line number Diff line
@@ -183,6 +183,13 @@ 
			status = "disabled";

		};



		exti: interrupt-controller@5000d000 {

			compatible = "st,stm32mp1-exti", "syscon";

			interrupt-controller;

			#interrupt-cells = <2>;

			reg = <0x5000d000 0x400>;

		};



		usart1: serial@5c000000 {

			compatible = "st,stm32h7-uart";

			reg = <0x5c000000 0x400>;