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Commit da7e29bd authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: use drm_i915_private everywhere in the power domain api 



The power domains framework is internal to the i915 driver, so pass
drm_i915_private instead of drm_device to its functions.

Also remove a dangling intel_set_power_well() declaration.

No functional change.

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 7e696e4c

drivers/gpu/drm/i915/i915_dma.c

+7 −7
Original line number Diff line number Diff line
@@ -1325,7 +1325,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	if (ret)

		goto cleanup_gem_stolen;



	intel_power_domains_init_hw(dev);

	intel_power_domains_init_hw(dev_priv);



	/* Important: The output setup functions called by modeset_init need

	 * working irqs for e.g. gmbus and dp aux transfers. */
@@ -1343,7 +1343,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	/* FIXME: do pre/post-mode set stuff in core KMS code */

	dev->vblank_disable_allowed = true;

	if (INTEL_INFO(dev)->num_pipes == 0) {

		intel_display_power_put(dev, POWER_DOMAIN_VGA);

		intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

		return 0;

	}
@@ -1381,7 +1381,7 @@ static int i915_load_modeset_init(struct drm_device *dev) 
	WARN_ON(dev_priv->mm.aliasing_ppgtt);

	drm_mm_takedown(&dev_priv->gtt.base.mm);

cleanup_power:

	intel_display_power_put(dev, POWER_DOMAIN_VGA);

	intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);

	drm_irq_uninstall(dev);

cleanup_gem_stolen:

	i915_gem_cleanup_stolen(dev);
@@ -1702,7 +1702,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
			goto out_gem_unload;

	}



	intel_power_domains_init(dev);

	intel_power_domains_init(dev_priv);



	if (drm_core_check_feature(dev, DRIVER_MODESET)) {

		ret = i915_load_modeset_init(dev);
@@ -1731,7 +1731,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	return 0;



out_power_well:

	intel_power_domains_remove(dev);

	intel_power_domains_remove(dev_priv);

	drm_vblank_cleanup(dev);

out_gem_unload:

	if (dev_priv->mm.inactive_shrinker.scan_objects)
@@ -1781,8 +1781,8 @@ int i915_driver_unload(struct drm_device *dev) 
	/* The i915.ko module is still not prepared to be loaded when

	 * the power well is not enabled, so just enable it in case

	 * we're going to unload/reload. */

	intel_display_set_init_power(dev, true);

	intel_power_domains_remove(dev);

	intel_display_set_init_power(dev_priv, true);

	intel_power_domains_remove(dev_priv);



	i915_teardown_sysfs(dev);

drivers/gpu/drm/i915/i915_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -434,7 +434,7 @@ static int i915_drm_freeze(struct drm_device *dev) 
	/* We do a lot of poking in a lot of registers, make sure they work

	 * properly. */

	hsw_disable_package_c8(dev_priv);

	intel_display_set_init_power(dev, true);

	intel_display_set_init_power(dev_priv, true);



	drm_kms_helper_poll_disable(dev);
@@ -556,7 +556,7 @@ static int __i915_drm_thaw(struct drm_device *dev, bool restore_gtt_mappings) 
		mutex_unlock(&dev->struct_mutex);

	}



	intel_power_domains_init_hw(dev);

	intel_power_domains_init_hw(dev_priv);



	i915_restore_state(dev);

	intel_opregion_setup(dev);

drivers/gpu/drm/i915/i915_drv.h

+2 −2
Original line number Diff line number Diff line
@@ -1024,9 +1024,9 @@ struct i915_power_well { 
	int count;

	unsigned long domains;

	void *data;

	void (*set)(struct drm_device *dev, struct i915_power_well *power_well,

	void (*set)(struct drm_i915_private *dev_priv, struct i915_power_well *power_well,

		    bool enable);

	bool (*is_enabled)(struct drm_device *dev,

	bool (*is_enabled)(struct drm_i915_private *dev_priv,

			   struct i915_power_well *power_well);

};

drivers/gpu/drm/i915/intel_display.c

+14 −13
Original line number Diff line number Diff line
@@ -1122,7 +1122,7 @@ void assert_pipe(struct drm_i915_private *dev_priv, 
	if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)

		state = true;



	if (!intel_display_power_enabled(dev_priv->dev,

	if (!intel_display_power_enabled(dev_priv,

				POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {

		cur_state = false;

	} else {
@@ -6863,23 +6863,23 @@ static unsigned long get_pipe_power_domains(struct drm_device *dev, 
	return mask;

}



void intel_display_set_init_power(struct drm_device *dev, bool enable)

void intel_display_set_init_power(struct drm_i915_private *dev_priv,

				  bool enable)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (dev_priv->power_domains.init_power_on == enable)

		return;



	if (enable)

		intel_display_power_get(dev, POWER_DOMAIN_INIT);

		intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);

	else

		intel_display_power_put(dev, POWER_DOMAIN_INIT);

		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);



	dev_priv->power_domains.init_power_on = enable;

}



static void modeset_update_crtc_power_domains(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };

	struct intel_crtc *crtc;
@@ -6898,19 +6898,19 @@ static void modeset_update_crtc_power_domains(struct drm_device *dev) 
						crtc->config.pch_pfit.enabled);



		for_each_power_domain(domain, pipe_domains[crtc->pipe])

			intel_display_power_get(dev, domain);

			intel_display_power_get(dev_priv, domain);

	}



	list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {

		enum intel_display_power_domain domain;



		for_each_power_domain(domain, crtc->enabled_power_domains)

			intel_display_power_put(dev, domain);

			intel_display_power_put(dev_priv, domain);



		crtc->enabled_power_domains = pipe_domains[crtc->pipe];

	}



	intel_display_set_init_power(dev, false);

	intel_display_set_init_power(dev_priv, false);

}



static void haswell_modeset_global_resources(struct drm_device *dev)
@@ -6991,7 +6991,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
			pipe_config->cpu_transcoder = TRANSCODER_EDP;

	}



	if (!intel_display_power_enabled(dev,

	if (!intel_display_power_enabled(dev_priv,

			POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))

		return false;
@@ -7019,7 +7019,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, 
	intel_get_pipe_timings(crtc, pipe_config);



	pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);

	if (intel_display_power_enabled(dev, pfit_domain))

	if (intel_display_power_enabled(dev_priv, pfit_domain))

		ironlake_get_pfit_config(crtc, pipe_config);



	if (IS_HASWELL(dev))
@@ -11595,7 +11595,8 @@ intel_display_capture_error_state(struct drm_device *dev) 


	for_each_pipe(i) {

		error->pipe[i].power_domain_on =

			intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));

			intel_display_power_enabled_sw(dev_priv,

						       POWER_DOMAIN_PIPE(i));

		if (!error->pipe[i].power_domain_on)

			continue;
@@ -11633,7 +11634,7 @@ intel_display_capture_error_state(struct drm_device *dev) 
		enum transcoder cpu_transcoder = transcoders[i];



		error->transcoder[i].power_domain_on =

			intel_display_power_enabled_sw(dev,

			intel_display_power_enabled_sw(dev_priv,

				POWER_DOMAIN_TRANSCODER(cpu_transcoder));

		if (!error->transcoder[i].power_domain_on)

			continue;

drivers/gpu/drm/i915/intel_drv.h

+8 −9
Original line number Diff line number Diff line
@@ -732,7 +732,7 @@ ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, 
bool intel_crtc_active(struct drm_crtc *crtc);

void hsw_enable_ips(struct intel_crtc *crtc);

void hsw_disable_ips(struct intel_crtc *crtc);

void intel_display_set_init_power(struct drm_device *dev, bool enable);

void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);

int valleyview_get_vco(struct drm_i915_private *dev_priv);

void intel_mode_from_pipe_config(struct drm_display_mode *mode,

				 struct intel_crtc_config *pipe_config);
@@ -871,18 +871,17 @@ bool intel_fbc_enabled(struct drm_device *dev); 
void intel_update_fbc(struct drm_device *dev);

void intel_gpu_ips_init(struct drm_i915_private *dev_priv);

void intel_gpu_ips_teardown(void);

int intel_power_domains_init(struct drm_device *dev);

void intel_power_domains_remove(struct drm_device *dev);

bool intel_display_power_enabled(struct drm_device *dev,

int intel_power_domains_init(struct drm_i915_private *);

void intel_power_domains_remove(struct drm_i915_private *);

bool intel_display_power_enabled(struct drm_i915_private *dev_priv,

				 enum intel_display_power_domain domain);

bool intel_display_power_enabled_sw(struct drm_device *dev,

bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,

				    enum intel_display_power_domain domain);

void intel_display_power_get(struct drm_device *dev,

void intel_display_power_get(struct drm_i915_private *dev_priv,

			     enum intel_display_power_domain domain);

void intel_display_power_put(struct drm_device *dev,

void intel_display_power_put(struct drm_i915_private *dev_priv,

			     enum intel_display_power_domain domain);

void intel_power_domains_init_hw(struct drm_device *dev);

void intel_set_power_well(struct drm_device *dev, bool enable);

void intel_power_domains_init_hw(struct drm_i915_private *dev_priv);

void intel_enable_gt_powersave(struct drm_device *dev);

void intel_disable_gt_powersave(struct drm_device *dev);

void ironlake_teardown_rc6(struct drm_device *dev);