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Commit da1d39e3 authored by Simon Horman's avatar Simon Horman Committed by Paul Mundt
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mmc, sh: Move constants to sh_mmcif.h 



This moves some constants from sh_mmcif.c to sh_mmcif.h
so that they can be used in sh_mmcif_boot_init().

It also alters the definition of SOFT_RST_OFF from (0 << 31) to
~SOFT_RST_ON (= ~(1 << 31)). The former seems bogus.  The latter is
consistent with the code in sh_mmcif_boot_init().

Cc: Yusuke Goda <yusuke.goda.sx@renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>
Signed-off-by: default avatarSimon Horman <horms@verge.net.au>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent a7bcf21e

drivers/mmc/host/sh_mmcif.c

+0 −23
Original line number Original line Diff line number Diff line
@@ -62,25 +62,6 @@ 
/* CE_BLOCK_SET */

/* CE_BLOCK_SET */

#define BLOCK_SIZE_MASK		0x0000ffff

#define BLOCK_SIZE_MASK		0x0000ffff





/* CE_CLK_CTRL */

#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */

#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */

#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\

				 (1 << 9) | (1 << 8)) /* resp busy timeout */

#define SRWDTO_29		((1 << 7) | (1 << 6) |		\

				 (1 << 5) | (1 << 4)) /* read/write timeout */

#define SCCSTO_29		((1 << 3) | (1 << 2) |		\

				 (1 << 1) | (1 << 0)) /* ccs timeout */



/* CE_BUF_ACC */

#define BUF_ACC_DMAWEN		(1 << 25)

#define BUF_ACC_DMAREN		(1 << 24)

#define BUF_ACC_BUSW_32		(0 << 17)

#define BUF_ACC_BUSW_16		(1 << 17)

#define BUF_ACC_ATYP		(1 << 16)



/* CE_INT */

/* CE_INT */

#define INT_CCSDE		(1 << 29)

#define INT_CCSDE		(1 << 29)

#define INT_CMD12DRE		(1 << 26)

#define INT_CMD12DRE		(1 << 26)
@@ -165,10 +146,6 @@ 
				 STS2_AC12BSYTO | STS2_RSPBSYTO |	\

				 STS2_AC12BSYTO | STS2_RSPBSYTO |	\

				 STS2_AC12RSPTO | STS2_RSPTO)

				 STS2_AC12RSPTO | STS2_RSPTO)





/* CE_VERSION */

#define SOFT_RST_ON		(1 << 31)

#define SOFT_RST_OFF		(0 << 31)



#define CLKDEV_EMMC_DATA	52000000 /* 52MHz */

#define CLKDEV_EMMC_DATA	52000000 /* 52MHz */

#define CLKDEV_MMC_DATA		20000000 /* 20MHz */

#define CLKDEV_MMC_DATA		20000000 /* 20MHz */

#define CLKDEV_INIT		400000   /* 400 KHz */

#define CLKDEV_INIT		400000   /* 400 KHz */

include/linux/mmc/sh_mmcif.h

+34 −5
Original line number Original line Diff line number Diff line
@@ -59,6 +59,29 @@ struct sh_mmcif_plat_data { 
#define MMCIF_CE_HOST_STS2	0x0000004C

#define MMCIF_CE_HOST_STS2	0x0000004C

#define MMCIF_CE_VERSION	0x0000007C

#define MMCIF_CE_VERSION	0x0000007C





/* CE_BUF_ACC */

#define BUF_ACC_DMAWEN		(1 << 25)

#define BUF_ACC_DMAREN		(1 << 24)

#define BUF_ACC_BUSW_32		(0 << 17)

#define BUF_ACC_BUSW_16		(1 << 17)

#define BUF_ACC_ATYP		(1 << 16)



/* CE_CLK_CTRL */

#define CLK_ENABLE		(1 << 24) /* 1: output mmc clock */

#define CLK_CLEAR		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define CLK_SUP_PCLK		((1 << 19) | (1 << 18) | (1 << 17) | (1 << 16))

#define SRSPTO_256		((1 << 13) | (0 << 12)) /* resp timeout */

#define SRBSYTO_29		((1 << 11) | (1 << 10) |	\

				 (1 << 9) | (1 << 8)) /* resp busy timeout */

#define SRWDTO_29		((1 << 7) | (1 << 6) |		\

				 (1 << 5) | (1 << 4)) /* read/write timeout */

#define SCCSTO_29		((1 << 3) | (1 << 2) |		\

				 (1 << 1) | (1 << 0)) /* ccs timeout */



/* CE_VERSION */

#define SOFT_RST_ON		(1 << 31)

#define SOFT_RST_OFF		~SOFT_RST_ON



static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)

static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)

{

{

	return readl(addr + reg);

	return readl(addr + reg);
@@ -149,17 +172,23 @@ static inline void sh_mmcif_boot_init(void __iomem *base) 




	/* reset */

	/* reset */

	tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);

	tmp = sh_mmcif_readl(base, MMCIF_CE_VERSION);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | 0x80000000);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp | SOFT_RST_ON);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & ~0x80000000);

	sh_mmcif_writel(base, MMCIF_CE_VERSION, tmp & SOFT_RST_OFF);





	/* byte swap */

	/* byte swap */

	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, 0x00010000);

	sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);





	/* Set block size in MMCIF hardware */

	/* Set block size in MMCIF hardware */

	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);

	sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);





	/* Enable the clock, set it to Bus clock/256 (about 325Khz)*/

	/* Enable the clock, set it to Bus clock/256 (about 325Khz).

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL, 0x01072fff);

	 * It is unclear where 0x70000 comes from or if it is even needed.

	 * It is there for byte-compatibility with code that is known to

	 * work.

	 */

	sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,

			CLK_ENABLE | SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 |

			SCCSTO_29 | 0x70000);





	/* CMD0 */

	/* CMD0 */

	sh_mmcif_boot_cmd(base, 0x00000040, 0);

	sh_mmcif_boot_cmd(base, 0x00000040, 0);