Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit da091653 authored by Russell King's avatar Russell King Committed by Russell King
Browse files

[ARM] Convert set_pte_ext implementions to macros 



There are actually only four separate implementations of set_pte_ext.
Use assembler macros to insert code for these into the proc-*.S files.

Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 1ad77a87

arch/arm/mm/proc-arm1020.S

+1 −23
Original line number Diff line number Diff line
@@ -399,29 +399,7 @@ ENTRY(cpu_arm1020_switch_mm) 
	.align	5

ENTRY(cpu_arm1020_set_pte_ext)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY



	bic	r2, r1, #PTE_SMALL_AP_MASK

	bic	r2, r2, #PTE_TYPE_MASK

	orr	r2, r2, #PTE_TYPE_SMALL



	tst	r1, #L_PTE_USER			@ User?

	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW



	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?

	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW



	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?

	movne	r2, #0



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	eor	r3, r1, #0x0a			@ C & small page?

	tst	r3, #0x0b

	biceq	r2, r2, #4

#endif

	str	r2, [r0]			@ hardware version

	armv3_set_pte_ext

	mov	r0, r0

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 4

arch/arm/mm/proc-arm1020e.S

+1 −23
Original line number Diff line number Diff line
@@ -383,29 +383,7 @@ ENTRY(cpu_arm1020e_switch_mm) 
	.align	5

ENTRY(cpu_arm1020e_set_pte_ext)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY



	bic	r2, r1, #PTE_SMALL_AP_MASK

	bic	r2, r2, #PTE_TYPE_MASK

	orr	r2, r2, #PTE_TYPE_SMALL



	tst	r1, #L_PTE_USER			@ User?

	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW



	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?

	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW



	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?

	movne	r2, #0



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	eor	r3, r1, #0x0a			@ C & small page?

	tst	r3, #0x0b

	biceq	r2, r2, #4

#endif

	str	r2, [r0]			@ hardware version

	armv3_set_pte_ext

	mov	r0, r0

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

arch/arm/mm/proc-arm1022.S

+1 −23
Original line number Diff line number Diff line
@@ -365,29 +365,7 @@ ENTRY(cpu_arm1022_switch_mm) 
	.align	5

ENTRY(cpu_arm1022_set_pte_ext)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY



	bic	r2, r1, #PTE_SMALL_AP_MASK

	bic	r2, r2, #PTE_TYPE_MASK

	orr	r2, r2, #PTE_TYPE_SMALL



	tst	r1, #L_PTE_USER			@ User?

	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW



	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?

	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW



	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?

	movne	r2, #0



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	eor	r3, r1, #0x0a			@ C & small page?

	tst	r3, #0x0b

	biceq	r2, r2, #4

#endif

	str	r2, [r0]			@ hardware version

	armv3_set_pte_ext

	mov	r0, r0

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

arch/arm/mm/proc-arm1026.S

+1 −23
Original line number Diff line number Diff line
@@ -354,29 +354,7 @@ ENTRY(cpu_arm1026_switch_mm) 
	.align	5

ENTRY(cpu_arm1026_set_pte_ext)

#ifdef CONFIG_MMU

	str	r1, [r0], #-2048		@ linux version



	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY



	bic	r2, r1, #PTE_SMALL_AP_MASK

	bic	r2, r2, #PTE_TYPE_MASK

	orr	r2, r2, #PTE_TYPE_SMALL



	tst	r1, #L_PTE_USER			@ User?

	orrne	r2, r2, #PTE_SMALL_AP_URO_SRW



	tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?

	orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW



	tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young?

	movne	r2, #0



#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH

	eor	r3, r1, #0x0a			@ C & small page?

	tst	r3, #0x0b

	biceq	r2, r2, #4

#endif

	str	r2, [r0]			@ hardware version

	armv3_set_pte_ext

	mov	r0, r0

#ifndef CONFIG_CPU_DCACHE_DISABLE

	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry

arch/arm/mm/proc-arm6_7.S

+5 −20
Original line number Diff line number Diff line
@@ -20,6 +20,8 @@ 
#include <asm/pgtable.h>

#include <asm/ptrace.h>



#include "proc-macros.S"



ENTRY(cpu_arm6_dcache_clean_area)

ENTRY(cpu_arm7_dcache_clean_area)

		mov	pc, lr
@@ -218,24 +220,7 @@ ENTRY(cpu_arm7_switch_mm) 
ENTRY(cpu_arm6_set_pte_ext)

ENTRY(cpu_arm7_set_pte_ext)

#ifdef CONFIG_MMU

		str	r1, [r0], #-2048		@ linux version



		eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY



		bic	r2, r1, #PTE_SMALL_AP_MASK

		bic	r2, r2, #PTE_TYPE_MASK

		orr	r2, r2, #PTE_TYPE_SMALL



		tst	r1, #L_PTE_USER			@ User?

		orrne	r2, r2, #PTE_SMALL_AP_URO_SRW



		tst	r1, #L_PTE_WRITE | L_PTE_DIRTY	@ Write and Dirty?

		orreq	r2, r2, #PTE_SMALL_AP_UNO_SRW



		tst	r1, #L_PTE_PRESENT | L_PTE_YOUNG	@ Present and Young

		movne	r2, #0



		str	r2, [r0]			@ hardware version

	armv3_set_pte_ext wc_disable=0

#endif /* CONFIG_MMU */

	mov	pc, lr