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Commit d9e2e014 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Joonas Lahtinen
Browse files

drm/i915/guc: Move doc near related definitions 



After GuC code reorg some documentation was left in wrong
place. Move it closer to corresponding definitions.

v2: use consistent name for the GuC (Sagar)

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: default avatarSagar Arun Kamble <sagar.a.kamble@intel.com>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171016144724.17244-5-michal.wajdeczko@intel.com
parent fdc6d731

drivers/gpu/drm/i915/intel_guc.h

+11 −0
Original line number Diff line number Diff line
@@ -33,6 +33,11 @@ 
#include "i915_guc_reg.h"

#include "i915_vma.h"



/*

 * Top level structure of GuC. It handles firmware loading and manages client

 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy

 * ExecList submission.

 */

struct intel_guc {

	struct intel_uc_fw fw;

	struct intel_guc_log log;
@@ -83,6 +88,12 @@ static inline void intel_guc_notify(struct intel_guc *guc) 
	guc->notify(guc);

}



/*

 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),

 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is

 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects

 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.

 */

static inline u32 guc_ggtt_offset(struct i915_vma *vma)

{

	u32 offset = i915_ggtt_offset(vma);

drivers/gpu/drm/i915/intel_guc_loader.c

+0 −23
Original line number Diff line number Diff line
@@ -29,29 +29,6 @@ 
#include "i915_drv.h"

#include "intel_uc.h"



/**

 * DOC: GuC-specific firmware loader

 *

 * intel_guc:

 * Top level structure of guc. It handles firmware loading and manages client

 * pool and doorbells. intel_guc owns a i915_guc_client to replace the legacy

 * ExecList submission.

 *

 * Firmware versioning:

 * The firmware build process will generate a version header file with major and

 * minor version defined. The versions are built into CSS header of firmware.

 * i915 kernel driver set the minimal firmware version required per platform.

 * The firmware installation package will install (symbolic link) proper version

 * of firmware.

 *

 * GuC address space:

 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),

 * which is reserved for Boot ROM, SRAM and WOPCM. Currently this top address is

 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects

 * used by GuC is pinned with PIN_OFFSET_BIAS along with size of WOPCM.

 *

 */



#define SKL_FW_MAJOR 6

#define SKL_FW_MINOR 1

drivers/gpu/drm/i915/intel_uc_fw.h

+5 −0
Original line number Diff line number Diff line
@@ -50,6 +50,11 @@ struct intel_uc_fw { 
	enum intel_uc_fw_status fetch_status;

	enum intel_uc_fw_status load_status;



	/*

	 * The firmware build process will generate a version header file with major and

	 * minor version defined. The versions are built into CSS header of firmware.

	 * i915 kernel driver set the minimal firmware version required per platform.

	 */

	u16 major_ver_wanted;

	u16 minor_ver_wanted;

	u16 major_ver_found;